Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-01-11
2003-07-01
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185090
Reexamination Certificate
active
06587372
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory devices with storage cells capable of storing more than one bit of data, i.e., more than two voltage levels. More particularly, the present invention is a memory device with storage cells capable of storing 1.5 bits of data, or three voltage levels, and methods using same.
BACKGROUND OF THE INVENTION
Most conventional memory devices, including programmable read-only memory (PROM), electrically-erasable PROM (EEPROM), flash EEPROM, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM) and the like, are capable of storing a single bit of data in a single memory cell. The memory cell of a conventional memory device may represent a data bit with a logical state of true or high voltage in the presence of stored charge in the memory cell. Conversely, the absence of charge may be representative of a data bit with a logical state false or low voltage.
Memory devices with more than one bit of data per cell are also known in the art. For example, U.S. Pat. No. 5,043,940 to Harrari defines multilevel states in a single memory cell in terms of the threshold voltage V
t
of a split-channel flash EEPROM memory cell. Harrari discloses using four discrete voltage levels to store two bits of data per memory cell by applying multiple programming pulses to each memory cell. U.S. Pat. No. 5,163,021 to Mehrota et al. also discloses a multi-level memory system wherein each memory cell is capable of four threshold voltage levels.
U.S. Pat. No. 5,566,125 to Fazio et al. discloses a method and circuitry for storing discrete amounts of charge in a single flash memory cell. Fazio et al. also discloses programming a flash memory cell to one of at least three amounts of charge, wherein the amount of charge placed in the flash memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.
U.S. Pat. No. 5,574,879 to Wells et al. discloses addressing modes for a dynamic single bit per cell to multiple bit per cell memory. Wells et al. also discloses a memory system containing switch control for selecting between standard cell addressing modes and multi-level cell addressing modes. U.S. Pat. No. 5,594,691 to Bashir discloses address transition detection sensing circuitry for flash memory having multi-bit cells and methods for using same. U.S. Pat. No. 5,612,912 to Gillingham discloses a method of sensing and restoring voltages in a multi-level DRAM cell.
However, none of these patents appears to disclose memory devices, apparatuses, systems and methods of using multi-bit memory cells to provide parity bits or methods of storing and retrieving partial bits of data from a single memory cell. Thus, there exists a need in the art for memory devices, apparatuses, systems and methods of using multi-bit memory cells to provide parity bits in a memory device based on multiples of 8 bits.
SUMMARY OF THE INVENTION
The present invention comprises memory devices, apparatuses and systems including multiple bit per cell memory cells and methods for using same. The multiple bit per cell memory cells of the present invention have higher memory densities than conventional single bit per cell memory cells. Additionally, spare states in multiple bit per cell memory devices that remain unmapped to binary data bits may be advantageously used for storing information. While multiple bit per cell memory cells having more than three states are contemplated, a memory cell with three states is preferable to a memory cell with four or more states because of the added difficulty in distinguishing four or more memory states in a given voltage range versus only three states, i.e., reliability decreases with narrower voltage margins between cell states.
An embodiment of a multiple bit per cell memory device in accordance with the present invention includes a command and address decode block connected to a command bus and an address bus, a data input/output (I/O) block connected to the command and address decode block and connected to a data bus, and a memory array of multiple bit memory cells connected to the command and address decode block and the data I/O block.
An embodiment of a memory card in accordance with the present invention includes a substrate for mounting and interconnecting integrated circuits, and at least one multiple bit per cell memory device integrated circuit mounted on the substrate, wherein the at least one multiple bit per cell memory device integrated circuit includes a command and address decode block connected to a command bus and an address bus, a data input/output (I/O) block connected to the command and address decode block and connected to a data bus, and a memory array of multiple bit memory cells connected to the command and address decode block and the data I/O block.
An embodiment of a computer system in accordance with the present invention includes an input device, an output device, a processor connected to the input device and the output device, a memory device connected to the processor device and including at least one multiple bit per cell memory device, wherein each of the at least one multiple bit per cell memory device includes a command and address decode block connected to a command bus and an address bus, a data input/output (I/O) block connected to the command and address decode block and connected to a data bus, and a memory array of multiple bit memory cells connected to the command and address decode block and the data I/O block.
An embodiment of a semiconductor substrate in accordance with the present invention includes at least one multiple bit per cell memory device mounted on the substrate, wherein the at least one multiple bit per cell memory device includes a command and address decode block connected to a command bus and an address bus, a data input/output (I/O) block connected to the command and address decode block and connected to a data bus, and a memory array of multiple bit memory cells connected to the command and address decode block and the data I/O block.
A method embodiment for mapping states of a multiple bit per cell memory device to binary data bits is disclosed. Method embodiments for operating a multiple bit per cell memory device are also disclosed.
These devices, apparatuses, systems and methods and attendant advantages of the present invention will be readily understood by reading the following detailed description in conjunction with the accompanying figures of the drawings.
REFERENCES:
patent: 4415992 (1983-11-01), Adlhoch
patent: 5043940 (1991-08-01), Harari
patent: 5163021 (1992-11-01), Mehrotra
patent: 5283761 (1994-02-01), Gillingham
patent: 5440505 (1995-08-01), Fazio et al.
patent: 5455801 (1995-10-01), Blodgett et al.
patent: 5515317 (1996-05-01), Wells et al.
patent: 5566125 (1996-10-01), Fazio et al.
patent: 5574879 (1996-11-01), Wells et al.
patent: 5594691 (1997-01-01), Bashir
patent: 5596526 (1997-01-01), Assar et al.
patent: 5612912 (1997-03-01), Gillingham
patent: 5905673 (1999-05-01), Khan
patent: 6260102 (2001-07-01), Robinson
Micro)n Technology, Inc.
Phan Trong
TraskBritt
LandOfFree
Memory device with multi-level storage cells and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory device with multi-level storage cells and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device with multi-level storage cells and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3054269