Majority filter counter circuit

Details Majority filter counter circuit Majority filter counter circuit

2001-08-27

2003-04-29

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Determining machine or apparatus operating time or...

C377S045000, C327S003000, C327S005000, C327S007000, C327S012000, C327S153000, C327S161000, C327S241000, C327S279000, C327S286000, C327S292000, C327S552000

Reexamination Certificate

active

06556643

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated memory circuits. More specifically, it relates to an improved digital delay locked loop (DDLL) circuit containing a buffer circuit for delaying the shifting of an output signal of the DDLL.
2. Description of Prior Art
Many high speed electronic systems possess critical timing requirements which dictate the need to generate a periodic clock wave form that possesses a precise time relationship with respect to some reference signal. The improved performance of computing integrated circuits (ICs) and the growing trend to include several computing devices on the same board present a challenge with respect to synchronizing the time frames of all the components.
While the operation of all components in the system should be highly synchronized, i.e., the maximum skew or difference in time between the significant edges of the internally generated clocks of all the components should be minute, it is not enough to feed the reference clock of the system to all the components. This is because different chips may have different manufacturing parameters which, when taken together with additional factors such as ambient temperature, voltage, and processing variations, may lead to large differences in the phases of the respective chip generated clocks.
Conventionally, synchronization is achieved by using DDLL circuits to detect the phase difference between clock signals of the same frequency and produce a digital signal related to the phase difference. By feeding back the phase difference-related signal to control a delay line, the timing of one clock signal is advanced or delayed until its rising edge is coincident, or within an acceptable range of coincidence, with the rising edge of a second clock signal.
The operation of conventional DDLLs is shown in
FIGS. 1 and 2
. In
FIG. 1
, clock input buffer
104
, delay lines
101
,
102
, and data output buffer
109
constitute an internal clock path. Delay line
101
is a variable delay generator with a logic-gate chain. A second delay line
102
is connected to replica circuits
108
, which emulate the internal clock path components. Replica circuits
108
include dummy output buffer
110
, with dummy load capacitance
111
and dummy clock buffer
107
. The dummy components and second delay line
102
constitute a dummy clock path having close to the same delay time as the internal clock path. Shift register
103
is used for activating a number of delay elements in both delay lines based on a command generated by phase detector
106
.
Phase detector
106
compares the dummy clock and the external clock phases which differ by at least one cycle. This comparison is illustrated in FIGS.
2
(
a
),
2
(
b
),
2
(
c
), and
2
(
d
). External clock signal
200
is divided down in divider
105
to produce divided-down external signal
201
. Signal
202
is the signal at the output of dummy delay line
102
. Signal
203
, which is generated inside phase comparator
106
, is a one delay unit delayed output dummy line signal
202
. If both signals
202
and
203
go high before
201
goes low, this means that the output clock is too fast and phase comparator
106
outputs a shift left (SL) command to shift register
103
, as illustrated in FIG.
2
(
b
). Shift register
103
shifts the tap point of delay lines
102
and
101
by one step to the left, increasing the delay. Conversely, if both signals
202
and
203
go high after
201
goes low, this means that the output clock is too slow and phase detector
106
outputs a shift right (SR) command to shift register
103
, as illustrated in FIG.
2
(
d
). Shift register
103
shifts the tap point of delay lines
102
and
101
by one step to the right, decreasing the delay. If
201
goes low between the time
202
and
203
go high, the internal cycle time is properly adjusted and no shift command is generated, as illustrated in FIG.
2
(
c
).The output of the internal clock path in this case coincides with the rising edge of the external clock and is independent of external factors such as ambient temperature and processing parameters.
One of the problems associated with the present DLL circuits is that phase detectors (such as
106
) are susceptible to noise. This is particularly true in a memory circuit, such as a dynamic random access memory circuit, where many signal switching operations occur. For example, when a bank of memory is activated (e.g., for a memory read or write operation), it pulls down bus voltage which effects the operation of the phase detector
106
. In addition, other types of noise events can effect the phase detector
106
. The phase detector
106
detects a problem with the phase relationship between the delay line output DLOut and the delay line input DLIn in that the phase relationship is no longer a predetermined value. As a result, the phase detector
106
attempts to correct the perceived problem by sending either an SR or an SL command to the shift register
103
which, in turn, sends a corresponding SR or SL command to delay lines
102
and
101
so as to maintain the predetermined phase relationship.
The problem is that by the time the phase detector
106
has corrected the perceived problem by sending an SR or an SL command, the noise condition has ceased and no correction is needed. Therefore, by attempting to correct a perceived problem, the phase detector
106
overcompensates with an SR or SL and actually takes the two signals out of their predetermined phase relationship.
One solution that has been suggested is to add an N-bit shift register between the phase detector and the delay line when the register is initialized to the center. The shift left and shift right signals received from the phase detector cause the majority filter to shift left or right. If the phase detector detects the predetermined phase relationship, the majority filter shifts toward the center. If the majority filter reaches either the right or the left-most register, the delay line is shifted in the appropriate direction and the majority filter is reset to center. A problem with the proposed solution outlined above is that it can be implemented as a 16 bit filter which requires at least 32 flip-flop circuits which take up a great deal of die space.
What is needed is an improved DDLL circuit that can distinguish when an error detected in the phase relationship between DLOut and DLIn is due to a noise event or due to something more serious that requires an actual shifting of the output signal DLOut. Furthermore, the DDLL circuit would desirably take up very little die space in accomplishing the above.
SUMMARY OF THE INVENTION
The present invention overcomes the problems associated with the prior art by providing an improved DDLL containing a majority filter counter circuit that takes up comparatively little die space. The majority filter counter circuit is located between the phase detector and the shift register of the DDLL. The majority filter counter circuit receives shifting commands from the phase detector and filters the shift commands from reaching the shift register until a predetermined number (e.g., 16) have been received from the phase detector before transmitting a shift command (e.g., shift right (SR), shift left (SL), etc.) to the shift register. Once the shift register receives the shift command, the shift register directs the delay line to shift by one tap in either a right-shift or a left-shift direction depending upon the phase relationship between DLIn and DLOut. By waiting for 16 shift commands in the same direction, the majority filter counter circuit ensures that a premature shift command is not delivered to the shift register in the case of a noise event. That is, the phase difference between DLIn and DLOut must be significant enough to have delivered 16 shift commands of either shift right (SR) or shift left (SL) in order for the delay line to be shifted. Furthermore, the above is achieved with only four flip-flop circuits configured as a 4-bit counter.


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