Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-10-16
2003-05-06
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
Reexamination Certificate
active
06560164
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor memory device with an internal clock generating circuit embedded therein. More particularly, the present invention relates to a configuration of a clock generating circuit for generating a clock signal used for producing an internal voltage or for determining an internal timing in a non-volatile memory such as a flash EEPROM (electrically erasable and programmable read only memory).
2. Description of the Background Art
FIG. 23
is a diagram schematically showing an overall configuration of a flash EEPROM as an example of a conventional semiconductor integrated circuit device. Referring to
FIG. 23
, the semiconductor integrated circuit device includes: a memory array
900
having a plurality of non-volatile memory cells arranged in rows and columns; an X decoder
901
for selecting an addressed row in the memory array
900
; a Y decoder
902
for selecting an addressed column in the memory array
900
; and a source/well decoder
903
for selecting a source line and a well (substrate) region in the memory array
900
. In a data write (program)/erasure operation of a non-volatile memory cell, a voltage for write (program) or erasure is applied on a source, a gate and a substrate region of a selected non-volatile memory cell. The source/well decoder
903
selects a source line and a well region onto which the voltages necessary for the write (program: simply referred to write hereinafter)/erasure are applied.
The semiconductor integrated circuit device further includes: an address buffer
904
receiving an external address signal to generate an internal address signal based on the received external address signal depending on an operating mode; a write circuit/sense amplifier
905
for performing write/read of data; and a data buffer
906
for performing external input/output of data.
The address buffer
904
, in a normal data read mode, generates an internal address signal according to external address input to generate an internal address signal to the X decoder
901
, the Y decoder
902
, and the source/well decoder
903
. In a write/erase mode, the address buffer
904
selects address signals sequentially generated internally according to an external address to apply the selected address signals to the decoders
901
to
903
.
The write circuit/sense amplifier
905
includes: a write register circuit for sequentially storing write data received from a data input buffer included in the data buffer
906
in data write operation mode; and an external read sense amplifier for amplifying memory cell data read out from memory cells selected by the Y decoder
902
to apply the amplified data to a data output circuit included in the data buffer
906
in data read operation mode. The write circuit/sense amplifier
905
may include an internal read sense amplifier for internally reading out data for verification of write/erasure.
The semiconductor integrated circuit further includes: a write/erase control circuit
909
capturing an external command to generate internal control signals necessary in a specified operating mode under control of a control signal; a high voltage generating circuit
908
for generating a high voltage (a positive or negative high voltage) necessary in write/erase operation under control of the write/erase control circuit
909
; and a ring oscillator circuit
907
performing an oscillating operation under control of the write/erase control circuit
909
to generate a clock signal providing an operation timing for the write/erase control circuit
909
and being used in a high voltage generating operation of the high voltage generating circuit
908
.
The write/erase control circuit
909
determines whether an effective (valid) command is applied according to a specific control signal, such as a write enable signal /WE, to generate necessary control signals according to an operating mode specified by the effective command, for controlling the operations of the decoders
901
to
903
, the address buffer
904
, the write circuit/sense amplifier
905
and the data buffer
906
.
The address buffer
904
takes in an external address when an external control signal instructs that the semiconductor integrated circuit device is selected. The data buffer
906
also performs buffering of data read out by the write circuit/sense amplifier
905
to output the buffered data externally when the external control signal instructs data read.
In the semiconductor integrated circuit shown in
FIG. 23
, the ring oscillator circuit
907
performs an oscillating operation in a predetermined oscillating period to generate a master clock signal providing an operating timing of the write/erase control circuit
909
and further generates a pump clock signal necessary for a charge pump operation of the high voltage generating circuit
908
normally constituted of a charge pump circuit. Hence, in the ring oscillator circuit
907
, there are individually provided a circuit for generating a master clock signal and a circuit for generating a charge pumping clock signal.
With such ring oscillator circuit
907
provided internally, the number of pin terminals decreases and there is no need to drive an on-board interconnection line for transmitting an external clock signal, when compared with a configuration to which the external clock signal is applied, and the power consumption of the entire system is reduced. By operating the write/erasure control circuit
909
in synchronization with the master clock signal from the ring oscillator circuit
907
, various kinds of internal operation timings can be determined on the basis of the master clock signal, thereby enabling accurate setting of the internal timings.
FIG. 24
is a diagram representing an example of the configuration of a ring oscillator included in the ring oscillator circuit
907
shown in FIG.
23
. In
FIG. 24
, the ring oscillator circuit
907
includes: inverter chain including cascaded inverters IVa of (2n−1) stages; and an inverter IVb inverting an output signal from the last stage of the inverter chain to generate an output signal &phgr;OUT (clock signal).
The ring oscillator is constituted of the inverter chain including inverters IVa of an odd number of cascaded stages. In a case where an oscillating circuit is constituted of such inverter chain, a CMOS inverter formed of a P channel MOS transistor (an insulated gate field effect transistors) and an N channel MOS transistor is generally employed as each inverter IVa of the inverter chain and the inverter IVb.
In such a CMOS inverter, an operating characteristic of a MOS transistor has a temperature dependency. That is, in a MOS transistor, as temperature rises, each mobility of electrons and holes in a channel is made smaller (due to increased lattice vibration and/or lattice scattering), and thereby, a drain current Ids decreases. Hence, the operating characteristics of the CMOS inverter chain has such a temperature dependency that, charging and discharging speeds become faster as temperature falls and an oscillating period of the ring oscillator become shorter, while as temperature rises, the charging and discharging speeds of the inverter chain formed of inverters IVa becomes slower and an oscillating period thereof becomes longer.
FIG. 25
is a diagram representing an example of the configuration of the high voltage generating circuit
908
shown in FIG.
23
. In
FIG. 25
, the high voltage generating circuit
908
includes a charge pump
908
a
for generating a high voltage VP according to an output signal &phgr;OUT of a ring oscillator
907
a
included in the ring oscillator circuit
907
. The charge pump
908
a
utilizes a capacitor to perform a charge pump operation according to the output signal &phgr;OUT of the ring oscillator
907
a
for generating the high voltage VP. The high voltage generated by the high voltage generating circuit
908
may be a negative voltage. Even in a case of a high voltag
Kawai Shinji
Mihara Masaaki
McDermott & Will & Emery
Phan Trong
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