Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2001-02-13
2003-01-14
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S059000, C257S749000, C359S016000, C359S016000, C359S016000, C359S016000, C438S623000, C438S626000, C438S631000, C438S723000, C438S780000
Reexamination Certificate
active
06507045
ABSTRACT:
This invention relates to a liquid crystal display (LCD) having an increased pixel aperture ratio. More particularly, this invention relates to a liquid crystal display including an array of TFTs (and method of making same) wherein an insulating layer having a plurality of contact vias or apertures etched therein is disposed between the TFTs and the pixel electrodes so that the pixel electrodes of the display are permitted to overlap the row and column address lines without exposing the display to capacitive cross-talk.
BACKGROUND OF THE INVENTION
Active matrix liquid crystal display (AMLCD) devices are typically composed of a matrix of liquid crystal pixels arranged horizontally in rows and vertically in columns. Such devices typically include first and second opposing polarizers, a liquid crystal layer disposed between the polarizers, and substantially transparent electrodes mounted on opposite sides of the liquid crystal (LC) layer so as to selectively energize same in order to create an image for a viewer.
Electronic matrix arrays find considerable applications in AMLCDs. Such AMLCDs generally include X and Y (or row and column) address lines which are horizontally and vertically spaced apart and cross at an angle to one another thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. pixel) to be selectively addressed. These elements in many instances are liquid crystal display pixels or alternatively the memory cells of an electronically adjustable memory array.
Typically, a switching device such as a thin film transistor (TFT) is associated with each array element or pixel. The isolation device permit the individual pixels to be selectively addressed by the application of suitable potentials between respective pairs of the X and Y address lines. Thus, the TFTs act as switching elements for energizing corresponding pixel electrodes.
Amorphous silicon (a-Si) TFTs have found wide usage for isolation devices in LCD arrays. Structurally, TFTs generally include substantially co-planar source and drain electrodes, a semiconductor material (e.g. a-Si) disposed between the source and drain electrodes, and a gate electrode in proximity to the semiconductor but electrically insulated therefrom by a gate insulator. Current flow through the TFT between the source and drain is controlled by the application of voltage to the gate electrode. The voltage to the gate electrode produces an electric field which accumulates a charged region near the semiconductor-gate insulator interface. This charged region forms a current conducting channel in the semiconductor through which current is conducted.
Typically, pixel aperture ratios (i.e. pixel openings) in non-overlapping AMLCDs are only about 50%. As a result, either display luminance is limited or backlight power consumption is excessive, thereby precluding or limiting use in portable applications. Thus, it is known in the art that it is desirable to increase the pixel aperture ratio or pixel opening size of LCDs to as high a value as possible so as to circumvent these problems. The higher the pixel aperture ratio (or pixel opening size) of a display, the higher the display transmission. Thus, by increasing the pixel aperture ratio of a display, transmission may be increased using the same backlight power, or alternatively, the backlight power consumption may be reduced while maintaining the same display transmission.
Currently, a common way of making AMLCDs is to pattern the ITO pixel electrodes at a distance or gap of about 5-10 &mgr;m from the bus lines which results in the LC material in this gap area not being activateable. Thus, the black matrix is required on the passive plate to overlap the pixel electrodes by about 5-10 &mgr;m so as to avoid light leakage in these areas and to compensate for potential plate misalignment. Thus, there exists a need in the art to eliminate this problem while simultaneously increasing pixel size.
For example, “High-Aperture TFT Array Structures” by K. Suzuki discusses an LCD having an ITO shield plane configuration having a pixel aperture ratio of 40% and pixel electrodes which overlap signal bus lines. An ITO pattern in Suzuki located between the pixel electrodes and the signal lines functions as a ground plane so as to reduce coupling capacitance between the signal lines and the pixel electrode. Unfortunately, it is not always desirable to have a shield electrode disposed along the length of the signal lines as in Suzuki due to production and cost considerations. The disposition of the shield layer as described by Suzuki requires extra processing steps and thus presents yield problems. Accordingly, there exists a need in the art for a LCD with an increased pixel aperture ratio which does not require an ITO shield plane structure to be disposed between the signal lines and pixel electrode.
FIG. 1
is a side elevational cross-sectional view of prior art linear thin film transistor (TFT)
100
of U.S. Pat. No. 5,055,899. A plurality of TFTs
100
are typically arranged on transparent insulating substrate
101
in the form of a matrix array as set forth in the '899 patent. Each TFT
100
includes gate electrode
102
connected to gate address line
113
(see
FIG. 2
) extending in the row direction, drain electrode
106
connected to drain line
114
extending in the column direction, and source electrode
107
connected to transparent pixel electrode
110
independently formed in the pixel area defined between the array of gate lines
113
and drain lines
114
. Pixel electrode
110
operates in conjunction with an opposing common electrode (not shown) on the other side of the liquid crystal layer (not shown) so as to selectively drive the pixel enabling the respective polarizers to transmit or absorb light rays in order to create an image for the viewer. A TFT electrode, to which a data signal is supplied, will be referred to hereinafter as a drain electrode, while the TFT electrode attached to the pixel electrode will be referred to as a source electrode.
More specifically, as shown in prior art
FIGS. 1-2
, gate electrode
102
of prior art TFT
100
is formed on clear substrate
101
. Gate insulating film
103
, made of silicon oxide, for example, is formed or deposited on substrate
101
over top of gate electrode
102
. Semiconductor film
104
, made of amorphous silicon (a-Si), for example, is deposited on substrate
101
over top of gate insulating film
103
and gate
102
. Drain and source electrodes
106
and
107
respectively are deposited on substrate
101
over top of layers
103
and
104
. The linear-shaped source and drain electrodes are separated from one another by a predetermined distance forming TFT channel
105
. Drain and source electrodes
106
and
107
respectively utilize doped a-Si contact layers
106
a
and
107
a
in combination with drain-source metal layers
106
b
and
107
b
so as to form electrical connections with semiconductor layer
104
.
Insulating film
108
is deposited on substrate
101
over the source and drain electrodes to a thickness falling within the range of 2,000 to 8,000 Å, preferably about 3,000 Å. Insulating layer
108
may be an organic insulating film obtained by spin-coating and baking polyimide or an acrylic resin, or a silicon oxide inorganic insulating film (SOG film) obtained by spin-coating and baking a silanol compound. Subsequent to the deposition of insulating film
108
on the source and drain electrodes, vias
112
are formed in layer
108
for the purpose of allowing substantially transparent pixel electrodes
110
to contact source electrodes
107
. Thus, when a pixel electrode
110
is deposited and patterned over top of insulating layer
108
, a portion of it is formed in via
112
as shown in
FIG. 1
so as to contact source
107
at point
109
. Pixel electrode
110
may be indium-tin-oxide (ITO), for example, and is sputtered on the surface of insulating layer
108
and in via
112
to a thickness of about 1,000 Å.
As can be seen in
FIG. 2
, pixel electrod
Boer Willem den
Gu Tieer
Flynn Nathan J.
Forde Remmon R.
LG Philips LCD Co., Ltd.
McKenna Long & Aldridge LLP
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