Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-06-14
2003-05-13
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S277000, C257S528000, C257S531000, C257S533000
Reexamination Certificate
active
06563192
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor dies, also commonly referred to as “chips.” It is particularly directed to the fabrication of a capacitor on a semiconductor die, the term dice including not only singulated dies but also partial wafers and entire wafers from which dies may be separated.
2. State of the Art
Circuit boards and other carrier substrates or platforms, both single- and multi-level, are employed to mechanically support and electrically connect both active devices, such as semiconductor dies, as well as passive components, such as resistors, capacitors and inductors. Conventional chip on board (C.O.B.) assemblies typically include discrete components of both classes, e.g., resistors, capacitors, and inductors, as well as various solid state “chips” or “dies” hard wired, plugged, soldered, ball-bonded or otherwise electrically connected to a conductor network carried by a platform such as a card, board or other substrate. In the prior art, discrete capacitors as well as resistors and inductors are often required to be placed on the platform in combination with adjacent, associated semiconductor dice, for example in the construction of a single in-line memory module (SIMM). With the increased circuit densities required by ever-faster processors and larger memories, due to a generally fixed board or platform area, commonly termed “real estate” in the semiconductor industry, the use of discrete passive components is viewed as an undesirable but hitherto necessary waste of real estate which could otherwise be applied to better and higher uses. The only exception to the requirement for a discrete capacitor known to the inventors is the fabrication of a capacitor on the board to which chips or dies may be attached.
It should be noted that the discrete capacitors referenced above are chip- or die-level capacitors serving as protective, noise-reducing gateways between the die and the remainder of the circuit in the assembly. Such capacitors are to be distinguished from the cell capacitors employed in dynamic random access memory (DRAM) cells, each cell of which includes a transistor (MOSFET) and capacitor. U.S. Pat. Nos. 5,547,063; 5,457,065; 5,459,094 and 5,459,095 illustrate various constructions which provide capacitance for dynamic random access memory (DRAM) cells. In each instance, the capacitor construction is integrated into the cell itself. As noted, such capacitors simply provide the storage requirement of the cell. U.S. Pat. No. 5,461,536 similarly discloses the construction of planar storage capacitors in association with the cells of a DRAM chip. The method disclosed involves a sequence of deposition and etching steps which add both electrode and dielectric layers to chips constructed from inorganic oxides.
Semiconductor chips or dice are conventionally fabricated by a series of material deposition, removal and conversion steps to selectively add, remove and alter the state of silicon and various metals to form the end-product die. For example, materials may be deposited upon, removed from, or converted to a different structure on a region of a substrate, either to form conductive structures on that level (such as circuit traces or bond pads), to form insulative, dielectric or passivating structures, or to penetrate beneath and form inter-level conductive elements (such as contacts or vias) or active component segments (n- and p-doping by diffusion or ion implantation) of the semiconductor devices residing in the die. Stated simplistically from another perspective, a semiconductor die may be viewed as a stack of layers, any of which may function as a substrate for adjacent layers. Typically, layers containing active (transistors, diodes, memory cells) or passive (capacitors, resistors) electronic components are separated by dielectric layers to avoid electrical shorts.
There remains a need for a simple, low cost technique for incidentally constructing a capacitor on or within a die to replace the chip capacitor of a SIMM board or other assembly having a comparable need for a capacitive or other passive component in association with the die, and supplied in the prior art by a discrete structure connected to the same platform as the die.
SUMMARY OF THE INVENTION
According to the present invention, a capacitive element is fabricated directly as a layer, ideally the top conductive layer, of a semiconductor die, such as a dynamic random access memory (DRAM) chip. This construction approach avoids the necessity commonly confronted in C.O.B. technology for a capacitor chip (or equivalent discrete component) to be connected, as by solder paste or conductive epoxy, to the circuit board or other platform incorporating the die. Thus, each DRAM or other chip structure supported on a conductor. platform, such as a circuit board, is provided with an integral die-level gateway capacitor as well as a resistor, if required, for special applications.
The die-level gateway capacitive element of the invention may be constructed through conventional mask (positive or negative resist) techniques in an additive or subtractive manner and in single or parallel planes. Ideally, the organic die coat which may be conventionally present on a finished die is relied upon to function as the dielectric component of the capacitor. Some die fabricators employ such a die coat in all instances, while others employ a die coat only with an LOC (leads over chips) configuration. The die coat composition may be selected specifically for its dielectric properties. Certain preferred embodiments include other components, such as a resistor, in the mask pattern. In this fashion, pre-designed capacitance and resistance values can be furnished in the die itself.
Preferably, the gateway capacitor is formed on the upper, front or active surface of a die. However, it is sometimes permissible or preferred to form the capacitor on the normally unused back surface of the die or incorporate it within one or more layers within the die itself.
Placing the gateway capacitor on the die eliminates the need for capacitor-to-die traces on the circuit board required with prior art discrete decoupling capacitors. Noise generated by the circuitry, as “seen” by a chip, is reduced to the lowest possible level by locating the capacitor as the final barrier between the circuit board and the chip. Chip performance is thereby optimized. Moreover, forming a capacitor in this fashion may require no additional steps when done in a die fabrication process already involving terminal or bond pad construction. All that is required is to utilize an appropriately modified mask for the fabrication process, unless a die coat not normally on the die must be added. The capacitor may be laid out and constructed incidental to the construction or rerouting of other conductive elements during the fabrication process on any convenient layer of the die having an adequate area to accommodate the capacitor traces and intervening dielectric. For example, rerouting peripheral bond pads into an array pattern for flip-chip applications presents a design opportunity to incorporate a capacitor according to the invention.
Positive and negative, generally planar, laterally-extending capacitor electrodes may be formed on the die surface or other layer in any convenient pattern effective to achieve a desired capacitance, typically less than about 500 pF, and usually within the approximate range of about 100-200 pF. One suitable such pattern positions the electrodes in a single-layer, side-by-side serpentine configuration with a narrow dielectric space or region laterally separating the electrodes. The capacitor of this invention can alternatively be formed in a more traditional configuration with two facing conductive layers separated by a thin dielectric layer. This configuration requires less real estate on the die, but is otherwise generally not preferred, because it may require additional steps in the fabrication process to deposit the intermediate dielectric layer, as well as a second conductive la
TraskBritt
Vockrodt Jeff
Zarabian Amir
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