Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-10-30
2003-05-20
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S419000, C710S306000
Reexamination Certificate
active
06567414
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the communication between devices over bus and more particularly, to the control of a posted instruction over a bridge to exit from a deadlock condition.
2. Description of the Related Art
A computer system typically includes a number of devices that communicate over a “bus.” Bus communications within a computer system are governed by predetermined protocols. One such bus transfer protocol is the peripheral component interconnect (PCI) bus specification (PCI specification, Revision 2.1, published by the PCI Special Interest Group of Portland, Oreg.). Protocols such as the PCI specification include rules directed to preventing conflicting transactions, i.e., read and write operations, from being issued and locking up the bus, otherwise known as “deadlock.” Rules designed to prevent deadlock conditions are called deadlock avoidance rules.
Many computer systems are equipped with multiple buses to spread out the electrical load or the processing load. In such systems, a “bridge” couples a first bus to a second bus. The system may have multiple bridges depending on the number of buses in the system. In general, a bridge identifies a transaction initiated by a device on one of the buses with an address associated with a device on the other bus to which the bridge is coupled. The bridge transfers the command and any data associated with the transaction to the destination bus.
One transaction used in bus communication is a write command, which allows one of the components to write data to an address associated with another of the devices. When a device desires to write to another device, it arbitrates for ownership of the bus to which it is coupled and becomes the bus master. Once the device becomes the bus master, it issues the write command. When the write command is issued, the first device maintains ownership of the bus until the write command is completed.
In the case where the destination address of the write command is associated with a device connected to a bus other than the bus to which the initiating device is coupled, the command and data must first be transferred to the second bus before it can be completed. When the command is transferred to the destination bus, the bridge becomes the bus master of the destination bus and issues the write command to the second device. In this simplified example, the write command would not be completed until after the second device has accepted the write, and the bridge has sent an acknowledgment of the write back to the first device. Such an arrangement is inefficient in that the first device would maintain ownership of its associated bus until the second device accepted the write.
To improve the efficiency of writes across a bridge, a bridge may contain a posted write buffer. This buffer latches the command and data and allows the initiating the device to complete the write when the data is latched in the posted write buffer. The bridge then assumes responsibility for ensuring the completion of the write command. This allows the first bus to be released for further transactions while the bridge ensures completion of the write. To prevent deadlock related to posted writes, certain deadlock avoidance rules are necessary.
A potential problem may arise when the first device or another device initiates a read from the target of the posted write before the data is actually written to the target device. If this read were allowed to complete, the device initiating the read would not receive the freshest copy of the data stored at the target address. In order to prevent this undesirable situation, the bridge must flush all of the posted write buffer writes to their respective targets before a read is permitted on the bus containing the targeted devices. One way to ensure that a posted write buffer has been cleared is to initiate a read command from the target device. This will force the flushing of all posted write buffers that reside in bridges between the device requesting the read and the target device before the read is permitted to complete.
A problem exists with the posted write buffer system described above when, for some reason (e.g., device failure, software error), the target cannot complete the posted write transaction. Because the presence of data in the posted write buffer prevents commands such as read commands from being completed, the failure of the target to accept the posted write causes a deadlock condition. If the condition in the target device preventing it from accepting the posted write persists, the deadlock will prevent proper operation of the computer system resulting in the need for reset.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above by preventing the inability of a target device to complete a posted write from causing an unrecoverable deadlock condition.
SUMMARY OF THE INVENTION
In one aspect of the present invention, an bridge is provided for communicating between a first and a second bus. The bridge includes a first interface unit, a second interface unit and a buffer unit. The first interface unit is adapted to be coupled to the first bus. The second interface unit is adapted to be coupled to the second bus. The buffer unit is coupled to the first and second interface units. The buffer unit is adapted to receive a posted transaction from one of the first and second interface units. The buffer unit includes a posting buffer and a discard timer. The posting buffer is adapted to store the posted transaction. The discard timer is adapted to generate a discard timer expired signal after a predetermined time interval that the posted transaction has resided in the posting buffer.
In a second aspect of the present invention, a method is provided for exiting from a potential deadlock situation. The method includes posting a transaction, tracking the length of time the transaction has been posted, and discarding the transaction after a predetermined time interval that the transaction has been posted.
REFERENCES:
patent: 5790831 (1998-08-01), Lin et al.
patent: 5938739 (1999-08-01), Collins et al.
patent: 6035362 (2000-03-01), Goodrum et al.
Deng Feng
Kardach James P.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kizou Hassan
Pezzlo John
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