Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-03-23
2003-03-25
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S096000, C345S092000
Reexamination Certificate
active
06538630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving a liquid crystal panel and a liquid crystal display apparatus for displaying high-quality images when multicolor display or full-color display is performed or when the liquid crystal panel for displaying an image is increased in size.
2. Description of the Related Art
A conventional active-matrix liquid crystal display apparatus using a thin-film transistor (hereinafter, referred to as “TFT”) includes a liquid crystal panel comprising a plurality of pixels arranged in a matrix form, and a liquid crystal driving portion for supplying electric signals to the liquid crystal panel. The pixels each have a structure such that liquid crystal is sandwiched between a pixel electrode and a counter electrode. In addition to the plurality of pixels, the liquid crystal panel includes a plurality of scanning lines, a plurality of data lines and a plurality of TFTs. The pixel electrode in each pixel is connected to one of the data lines through one of TFTs. The counter electrodes of all the pixels are interconnected to one another to form one common electrode. The liquid crystal driving portion includes a gate driver for supplying electric signals to the scanning lines, a source driver for supplying electric signals to the data lines, and the common electrode.
FIG. 10
is a block diagram showing the electric structure of the source driver
1
. The source driver
1
includes an input latch circuit
2
, a shift register
3
, a sampling memory
4
, a hold memory
5
, a D/A converter
6
, a gradation-voltage-generating circuit
7
and an output circuit
8
. The source driver
1
is supplied with the image data representative of the image to be displayed. The image data comprises data for expressing the brightness, chroma and hue of each image element forming the image. Each image element of the image corresponds to a set of three pixels having red, blue and green color filters, respectively, in the liquid crystal panel. Therefore, each image element data comprises three kinds of gradation components, namely, so-called R (red), G (green) and B (blue) components, and the gradation components represent 64 levels of gradations.
First, the three kinds of gradation components in each image element data are successively supplied to the input latch circuit
2
to be latched. Based on a synchronizing signal SPI supplied from a control circuit disposed outside the source driver
1
through the shift register
3
that operates in response to a clock signal CK, the sampling memory
4
samples the image data latched by the input latch circuit
2
. Consequently, a part of the image data which part is associated with an electric signal to be supplied from the source driver
1
to the liquid crystal panel within a single horizontal period 1H, that is, a plurality of gradation components that decide the gradations of a plurality of pixels constituting one of the rows in the liquid crystal panel are stored in the sampling memory
4
. The plurality of gradation components are transferred from the sampling memory
4
to the hold memory
5
in synchronism with a synchronizing signal LS of the horizontal period of the liquid crystal panel.
The hold memory
5
latches the plurality of gradation components being transferred, and supplies the plurality of gradation components to the D/A converter
6
. The gradation-voltage-generating circuit
7
divides the difference between predetermined two reference voltages Vref
1
and Vref
2
, decides 64 kinds of gradation voltages and supplies the gradation voltages to the D/A converter. The gradation voltages each correspond to one of the 64 levels of gradations that the pixels can take. The D/A converter
6
selects from among the 64 kinds of gradation voltages the gradation voltages that correspond to the gradations shown by the plurality of gradation components being supplied, and supplies the selected gradation voltages to the output circuit
8
. The output circuit
8
impedance-converts the selected gradation voltages and charges or discharges the source lines of the liquid crystal panel in accordance with the impedance-converted gradation voltages. Consequently, to the source lines of the liquid crystal panel, electric signals of voltages based on the image data are supplied as so-called data signals.
In each of the pixels, since the pixel electrode and the counter electrode act as electrodes of a capacitor, a capacitance called, for example, parasitic capacitance is present. That is, data signals in accordance with the voltages to be held by the pixels are supplied from the source driver to the data lines and the states of the TFTs are changed, whereby the voltages can be written into the pixels so as to be held by the pixels.
For example, with respect to one of all the TFTs, when the voltage of an electric signal, namely, a so-called scanning signal, supplied from the gate driver to the scanning line to which the gate terminal of the TFT is connected becomes positive, a positive voltage is applied to the gate terminal, so that the one of the TFTs changes to a so-called ON state. Consequently, the pixel including the pixel electrode to which the one of the TFTs is connected is charged by the voltage applied to the data line to which the one of the TFTs is connected. When the voltage of the scanning signal becomes negative, a negative voltage is applied to the gate terminal, so that the one of the TFTs changes to so-called OFF state. Consequently, the voltage between the pixel electrode and the counter electrode in the pixel is maintained at the voltage applied between the pixel electrode and the counter electrode when the one of the TFTs changes to OFF state. As a result, the voltage to be held is written into the pixel. The transmittance of the liquid crystal layer in the pixel, that is, the gradation of the pixel is decided in accordance with the voltage held by the pixel. Therefore, by controlling the gradations of all the pixels in the liquid crystal panel by the voltages held by the pixels, an image is displayed on the liquid crystal panel.
The liquid crystal panel is reversely driven in order that the liquid crystal is not polarized. Reverse driving methods include a so-called dot reversal driving method and a so-called line reversal driving method. In the description that follows, it is assumed that the pixels of the liquid crystal panel are arranged in 6 rows and 5 columns.
First, the behavior of the liquid crystal display apparatus of the above-described structure when the liquid crystal display apparatus is driven by the line reversal driving method will be described.
FIG. 11
shows a timing chart of a plurality of scanning signals
11
a
to
11
f
supplied from the gate driver in the liquid crystal display apparatus to six scanning lines.
FIG. 12
shows a timing chart of one scanning signal
11
of the scanning signals
11
a
to
11
f
, one data signal
12
of a plurality of data signals supplied from the source driver
1
to five data lines, and a voltage
13
applied to the common electrode in the liquid crystal display apparatus.
FIGS. 11 and 12
will be described together.
The scanning signals
11
a
to
11
f
are held at high level during a predetermined single horizontal period WH at intervals of a predetermined frame display period CH, and are held at low level during the remaining period. The timing where the plurality of scanning signals
11
a
to
11
f
are held at high level within a time period corresponding to one cycle of a horizontal synchronization cycle differs among the signals. Therefore, to all the pixels in the row of pixels on one of the scanning lines, the voltage to be held is written while the scanning signal supplied to the one of the scanning lines is held at a high level. The row as pixels on one of the scanning lines is a set of a plurality of pixels including pixel electrodes connected to the drain terminals of a plurality of TFTs whose gate terminals are connected to the one of the scanning lines.
The cycle of the alterna
Tamai Shigeki
Tanaka Shigeki
Birch & Stewart Kolasch & Birch, LLP
Kumar Srilakshmi K
Saras Steven
Sharp Kabushiki Kaisha
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