Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-03-07
2003-09-09
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S532000, C257S506000, C257S508000, C257S524000, C438S957000
Reexamination Certificate
active
06617666
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2001-065253, filed Mar. 8, 2001, the entire contents of which are incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with an MIM (Metal Insulating Metal) capacitor, and a process for manufacturing the semiconductor device.
2. Description of the Related Art
Semiconductor devices provided with Cu wiring of a damascene structure and MIM capacitors are now available.
FIG. 28
is a sectional view of a conventional semiconductor device. As shown in
FIG. 28
, a via hole
43
and a wire
44
, which are made of, for example, Cu, are provided in a film
41
of a low dielectric constant and a film
42
of a high dielectric constant. A Cu-diffusion-preventing film
45
is provided on the high dielectric film
42
and wire
44
, and a capacitor
49
is provided on a selected portion of the Cu-diffusion-preventing film
45
. The capacitor
49
is formed of a lower electrode
46
, a dielectric film
47
and an upper electrode
48
. An insulating film
50
is provided on the capacitor
49
and Cu-diffusion-preventing film
45
. The surface of the insulating film is flattened by CMP (Chemical Mechanical Polishing).
In such conventional semiconductor devices, it is desirable that the insulating film
50
be formed of a low dielectric film in order to reduce the parasitic capacitance between wires.
However, since the low dielectric film is a rough film, a crack may occur if the surface of the film is flattened. Therefore, it is very difficult to level, by CMP, the surface of an insulating film
50
formed of a low dielectric film. To avoid this, a high dielectric film could be used as the insulating film
50
, as thus would reduce the formation of cracks under CMP.
However, since the capacitor
49
is provided on a selected portion of the Cu-diffusion-preventing film
45
, there is a step corresponding to the thickness of the capacitor
49
between the area provided with the capacitor and the area without. To eliminate the step caused by the presence of the capacitor
49
, it is necessary to form an insulating film
50
in the area with no capacitor on the Cu-diffusion-preventing film
45
. Thus, as stated above, a high dielectric film or insulating film
50
is provided on the film
45
to surround the capacitor
49
. The provision of the high dielectric insulating film
50
to fill the step caused by the capacitor
49
inevitably increases the parasitic capacitance between wiring layers.
As described above, in the conventional semiconductor device, it is very difficult to level the surface of the insulating film
50
by CMP.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a first insulating film comprising an opening; a capacitor formed at a selected position in the opening; a second insulating film formed at least in the opening; and a third insulating film formed on the second insulating film.
According to a second aspect of the present invention, there is provide a process of manufacturing a semiconductor device, comprising: forming a first insulating film; removing a selected portion of the first insulating film, thereby forming an opening; forming a capacitor at a selected position in the opening; forming a second insulating film at least in the opening; and forming a third insulating film on the second insulating film.
REFERENCES:
patent: 6226171 (2001-05-01), Beilin et al.
patent: 10-41481 (1998-02-01), None
Nakashima Yuichi
Yoshitomi Takashi
Flynn Nathan J.
Frommer & Lawrence & Haug LLP
Kabushiki Kaisha Toshiba
Pan Grace L.
Wilson Scott R.
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