Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1999-12-21
2003-04-01
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S689000, C438S737000
Reexamination Certificate
active
06541389
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of patterning a thin layer by wet etching. An array substrate for an active matrix type display device is constituted of a plurality of signal lines and gate wiring lines, which are arranged in a grid form on a transparent insulating substrate such as glass, and a thin film transistor (TFT) which is formed of a semiconductor film such as amorphous silicon (a-Si: H) serving as an active layer present near an intersection point at which the signal lines are crossed with the gate wiring lines.
In recent years, a method of forming a drive circuit integrally on the same array substrate, has been put in practical use, although it was used by being attached to the array substrate. As its active layer, a polycrystalline silicon (P—Si) or the like having a higher mobility than amorphous silicon is used.
In most cases, the TFT is formed into an inverted staggered type by providing a gate insulating film on gate wiring line, and then forming a semiconductor film, a source electrode and a drain electrode on the gate insulating film.
Various patterns corresponding to the gate wiring lines, gate insulating film, source electrode and drain electrode are formed in accordance with methods including wet etching and dry etching. The wet etching is widely employed in a planar display device since the structure of the device is simple and a large-area work piece can be etched uniformly with high rate.
However, in the case where the gate wiring lines of the inverted staggered type TFT is formed, the edge surface of the gate wiring lines must be processed into a taper form in order to insulate the gate wiring lines by the gate insulating film covering the gate wiring lines.
To overcome the aforementioned technical problem, Japanese Patent Application KOKAI publication Nos. 4-372934 and 9-064366 disclose a technique for forming the gate wiring lines into a taper form by use of the difference in etching rate. More specifically, the gate wiring lines are formed in a stacked-film structure consisting of an Al (aluminium) film and a Mo (molybdenum) film, etching is performed by using an acid mixture prepared by mixing phosphoric acid, acetic acid, and nitric acid in a predetermined ratio followed by adjusting the concentration of the mixture. In other words, according to the aforementioned publications, it is possible to insulate the gate electrode relatively easily without fail by forming the gate wiring line into a taper form by use of the difference in etching rate between the Al and Mo stacked films. Note that according to each of the publications, because of the wet etching, it is possible to sufficiently permeate an etching solution without being affected by the viscosity of the etching solution, with the result that a taper of a desired shape can be obtained.
However, in the manufacturing methods disclosed in the aforementioned publications, in the case where the viscosity of the etching solution is high, minute bubbles, which are generated by air entering into the etching solution at the time a substrate goes into the etching solution and generated by the reaction between the etching solution and a conductive thin layer, are not separated from the work piece to be etched on the pattern of the substrate and remain thereon.
Since the etching solution does not reach the portion on which the minute bubbles remain, Al and Mo stacked films are sometimes left without being etched.
The remaining Al and Mo stacked films not removed by etching causes short-circuit particularly in a portion densely patterned, for example, between the gate wiring lines arranged in a short distance. As a result, the yield of the product is significantly reduced.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of patterning a thin layer by using wet etching without a decrease in yield of a product due to the remaining pattern.
Another object of the present invention is to provide a method of patterning a thin layer in which an etching solution has a high degree of freedom.
A further object of the present invention is to provide a method of patterning a thin layer in which a large area can be uniformly etched.
The present invention provides a method of patterning a thin layer deposited on a substrate into a predetermined shape in accordance with a pattern layer disposed on the thin layer, comprising:
a first step of soaking the substrate into a first solution and etching off the thin layer in accordance with the pattern layer;
a second step of spraying a second solution onto the thin layer of the substrate, thereby the substrate is washed; and
a third step of soaking the substrate into a third solution and etching off the thin layer in accordance with the pattern layer.
REFERENCES:
patent: 4760351 (1988-07-01), Newell et al.
patent: 5633175 (1997-05-01), Kikuchi et al.
patent: 5858257 (1999-01-01), Naitoh
patent: 6004881 (1999-12-01), Bozada et al.
patent: 6225150 (2001-05-01), Lee et al.
patent: 04372934 (1992-12-01), None
patent: 09064366 (1997-03-01), None
Kubo Akira
Machida Masahiko
Mizouchi Kiyotsugu
Pillsbury & Winthrop LLP
Sarkar Asok Kumar
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