Semiconductor memory

Details Semiconductor memory Semiconductor memory

2001-03-19

2003-03-18

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230010, C365S063000, C365S206000, C365S205000, C365S051000

Reexamination Certificate

active

06535451

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory, and principally to a technology effective for application to one of such a type that a so-called one-intersection type memory array having dynamic memory cells placed at intersecting points of word lines and bit lines is used and a large number of banks are provided therein.
According to investigations subsequent to the completion of the present invention, it has been revealed that Japanese Patent Application Laid-Open No. Hei 4(1992)-134691 (hereinafter called “prior art 1”), Japanese Patent Application Laid-Open No. Hei 2(1990)-289988 (hereinafter called “prior art 2”), Japanese Patent Application Laid-Open No. Hei 9(1997)-213069 (hereinafter called “prior art 3”), Japanese Patent Application Laid-Open No. Hei 4(1992)-6692 (hereinafter called “prior art 4”) and Japanese Patent Application Laid-Open No. Hei 9(1997)-246482 (hereinafter called “prior art 5”) have existed as those considered to be related to the present invention to be described later. The publications according to the prior arts 1 through 5 respectively disclose those in which information storage capacitors using MOS capacity are used and open bit-line type (one-intersection type or system) sense amplifiers are alternately disposed. However, these publications no disclose consideration paid to a multibank-configured DRAM related to the invention of the present application to be described later in either case.
SUMMARY OF THE INVENTION
It has been desirable to reduce the cost of a dynamic RAM (hereinafter called simply “DRAM”). To this end, a reduction in chip size is most effective. A scale-down has heretofore been pushed forward to reduce a memory cell size. It is however necessary to change even an operating mode or system of a memory array and thereby make a further reduction in cell size. By changing the operating mode of the memory array from a two-intersection type to a one-intersection type, the cell size can ideally be reduced to 75% by using the same design rule. However, the one-intersection type memory array has a problem in that array noise placed on each bit line or the like is high as compared with the two-intersection type memory array.
On the other hand, a multibank-configured DRAM array is of increasing importance in a Rambus DRAM and a logic-mixed DRAM to improve system performance. It has been revealed that when a one-intersection type multi-bank DRAM is configured, the one-intersection type memory array has the problem in that the array noise placed on the bit line or the like is high as compared with the two-intersection type memory array as described above, and noise interference between adjacent mats presents a large problem for the multi-bank configuration. In addition to the above, an increase in chip area due to end mats, which takes place where sense amplifiers are alternately laid out under a one-intersection configuration, also offers a problem, thus leading to the realization of the present invention under discussion of a method of solving these problems, which is intended for the multibank-configured DRAM.
An object of the present invention is to provide a semiconductor memory of a multi-bank configuration, which has implemented high integration thereof and the stabilization of its operation. Another object of the present invention is to provide a semiconductor memory while provides ease of use while achieving high integration thereof and the stabilization of its operation. The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a typical one of the inventions disclosed in the present application will be described in brief as follows: A plurality of sense amplifier areas placed alternately with respect to a plurality of memory array areas placed along a first direction are provided. The plurality of memory array areas are respectively provided with a plurality of bit lines provided along the first direction, a plurality of word lines provided along a second direction intersecting the first direction, and a plurality of memory cells provided so as to correspond to portions where the plurality of bit lines and the plurality of word lines intersect. Sense amplifiers each of which receives therein a pair of signals from each of the bit lines extending to one of the memory array areas on both sides adjacent to the respective sense amplifier areas and each of the bit lines extending to the other thereof, are provided. Respective word-line selecting timings or addresses with respect to the two memory array areas away from each other with the two or more memory array areas interposed therebetween are independently set.
A summary of another typical one of the inventions disclosed in the present application will be explained in brief as follows: A plurality of sense amplifier areas placed alternately to a plurality of memory array areas placed along a first direction are provided. The plurality of memory array areas are respectively provided with a plurality of bit lines provided along the first direction, a plurality of word lines provided along a second direction intersecting the first direction, and a plurality of memory cells respectively provided in association with portions where the plurality of bit lines and the plurality of word lines intersect. Sense amplifiers each of which receives therein a pair of signals from each of the bit lines extending to one of the memory array areas on both sides adjacent to the respective sense amplifier areas and each of the bit lines extending to the other thereof, are provided. The two memory array areas provided adjacent to each other constitute one of a plurality of banks. Respective word-line selecting addresses with respect to two banks away from each other with one of the plurality of banks interposed therebetween are independently set.


REFERENCES:
patent: 5838038 (1998-11-01), Takashima et al.
patent: 5970003 (1999-10-01), Miyatake et al.
patent: 6088252 (2000-07-01), Fujisawa et al.
patent: 2001/0000691 (2001-05-01), Fujisawa et al.
patent: 2001/0028593 (2001-10-01), Sekiguchi et al.
patent: 2001/0040835 (2001-11-01), Fujisawa et al.
patent: 2002/0001215 (2002-01-01), Fujisawa et al.
patent: 4-6692 (1992-01-01), None
patent: 4-134691 (1992-05-01), None
patent: 9-213069 (1997-08-01), None
patent: 9-246482 (1997-09-01), None

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