Local substrate pumping in integrated circuits

Details Local substrate pumping in integrated circuits Local substrate pumping in integrated circuits

1996-06-18

2003-01-14

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S564000

Reexamination Certificate

active

06507235

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuit design, and more particularly to a method for locally charge pumping a substrate.
BACKGROUND OF THE INVENTION
It is sometimes advantageous to bias the substrate of an integrated circuit to a negative value. This is especially true of modern day Dynamic Random Access Memory (DRAM) devices. Typically DRAM devices contain circuits thereon which “charge pump” the substrate to a negative potential, without the need for an external negative voltage supply. The negative potential generated by a substrate charge pump is usually a function of the external supply. voltage which is introduced onto the chip (Vcc). For a Vcc of 5V, a negative substrate bias (Vbb) of perhaps −1.0V might be achieved. The maintenance of the negative potential is important to the functioning of the DRAM memory cells. Because the capacitors employed in the cells typically contain a bottom plate of polysilicon which is connected to an N-type region, biasing the P- substrate to a negative potential helps to keep the diode that is formed between the N-type region and the P- substrate in a reverse bias condition when either a logic ‘0’ (typically 0.0V) or a logic ‘1’ (typically Vcc) is stored on the capacitor. The reversed biased diode will reduce junction leakage to the substrate and therefore helps to effectively store the data state at the cell for a reasonable period of time.
However, the use of a negative substrate bias can limit the flexibility of a DRAM's other circuits. In particular, the negative substrate bias limits the voltages that can be employed in connection with the antifuse circuitry that appears in the peripheral circuitry on a DRAM. Typically, such antifuses are used as a type of destructive Read Only Memory (ROM), wherein the antifuses can be selectively destroyed, or “fused,” to encode particular information onto the chip. Such antifuses can be used, for example, to store a DRAM's identification number, or to control the redundancy circuitry which re-routes signals away from known failing memory locations to functional auxiliary memory locations located elsewhere on the DRAM.
Techniques for fabricating an antifuse dell are well-known in the art, and a stylized cross-section of a typical antifuse cell is shown in FIG.
1
. The antifuse
2
is serially connected to a programming transistor. Typically, the antifuse
2
is a capacitor, as shown in FIG.
1
. The programming transistor gate
4
, when biased to a high logic level, will cause a channel to form in the P- substrate
6
below the gate
4
, thereby allowing the voltage at node
8
to be passed through the channel to lower antifuse plate
10
. Although in reality the transistor gate
4
is separated from the substrate
6
by a dielectric, the dielectric is not shown in the stylized cross-section.
If the upper antifuse plate
12
is biased to a different voltage than lower antifuse plate
10
, a potential difference will form across the dielectric between upper antifuse plate
12
and lower antifuse plate
10
. If this potential difference exceeds the permissible field strength of the capacitor dielectric, the dielectric will break down and upper antifuse plate
12
and lower antifuse plate
10
will become fused together, creating a low-resistive path between the two plates.
A typical potential difference necessary to break down the capacitor dielectric may be, for example, 10V. In such a case, biasing upper antifuse plate
12
to 10V while grounding the lower antifuse plate
10
would be sufficient to short circuit the antifuse. However, design considerations may not favor the use of such a high voltage on the upper antifuse plate
12
. Because the external supply voltage (Vcc) is typically 5V or less, the 10V signal will need to be generated by the use of a charge pump, if the 10V signal is to be generated on the chip itself. Charge pumping may consume an undesirable amount of power, and the appearance of the 10V signal at other locations on the chip may cause other reliability problems.
It is advantageous to be able to apply a voltage more consistent with normal chip operation to the upper antifuse plate
12
, for example, 5V. However, this would mean that a −5V signal would need to be passed through the programming transistor to lower antifuse plate
10
to effect programming of the antifuse.
Although not shown in
FIG. 1
, a global substrate pumping circuit on DRAM devices is connected to the substrate
6
at node
14
, creating a voltage on substrate
6
which is typically around −1.0V. The global substrate pumping circuit is typically connected to the substrate
6
at several locations laterally across the chip to provide a uniform distribution of the negative potential across the substrate
6
. With a −1.7V potential on substrate
6
, a −5V signal cannot be passed to lower antifuse plate
10
, because the diode created between the N+region connected to node
8
and P- substrate
6
becomes forward biased before −5.0V can be achieved on the lower antifuse plate
10
. That diode will be forward biased when the voltage on the P side of the diode (substrate
6
) is a diode threshold voltage higher than the N side of the diode (node
8
). Because a typical P-N diode threshold voltage is approximately +0.7V, the lowest voltage that could appear at node
8
without creating a forward biased diode is approximately −1.7V, if the substrate
6
is biased to −1.0V. Forward biasing of the diode in this fashion is detrimental to circuit operation because it will cause excessive amounts of power to be consumed, and will load down the passed signal to a voltage approaching that of the substrate voltage, thus prohibiting the destruction of the antifuse.
The disclosed invention alleviates this problem by providing a bias to the substrate which is local to the substrate area encompassing the antifuses.
SUMMARY OF THE INVENTION
According to the present invention, a method is disclosed wherein the voltage of a semiconducting substrate can be locally pumped to a voltage different than the global voltage of the semiconducting substrate. The method may employ the use of a well to isolate the locally pumped voltage from the global substrate voltage, or may be employed without the use of isolation, relying instead on the natural resistance of the substrate. The use of this method can be used in the design of antifuses which employ the use of negative potentials during the programming of the antifuse, thereby reducing the need for producing high positive potentials on the chip. Furthermore, the method can be used to adjust the threshold voltage of selected transistors without fabricating the selected transistors by a process different from other non-selected transistors. Also, the method can be used to reduce the effects of CMOS latch-up. A pumping circuit for producing a suitable localized voltage is also disclosed and claimed.


REFERENCES:
patent: 5386135 (1995-01-01), Nakazato et al.
patent: 5394365 (1995-02-01), Tsukikawa
patent: 5473183 (1995-12-01), Yonemoto
patent: 5491359 (1996-02-01), May et al.
patent: 5497023 (1996-03-01), Nakazato et al.
patent: 5559356 (1996-09-01), Yukawa
patent: 5917354 (1999-06-01), Nakai et al.

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