Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
1999-06-25
2003-09-30
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189090, C365S189110, C365S194000, C365S207000, C365S208000
Reexamination Certificate
active
06628564
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having the function of executing a reset operation of a word line connected to a specific memory cell, by driving the word line, in order to return the specific memory cell, in a memory cell array of a semiconductor memory, from an activated state to a standby state.
Demands for lower power consumption have been increasing in recent years in semiconductor devices comprising a semiconductor memory such as a dynamic random access memory (hereinafter abbreviated to “DRAM”) in consideration of battery driving. Therefore, power that is consumed in a circuit for executing the reset operation described above must be reduced as much as possible.
The present invention also relates to a semiconductor device for shooting data by storing charges in memory cells and more specifically, to a semiconductor device which sets a word line potential at the time of non-selection to a negative potential so as to insure a safe and reliable operation even when a power source voltage is lowered so as to cope with higher circuit integration and even when a transistor threshold voltage value becomes low.
The present invention also relates to a semiconductor device including a plurality of power source circuits for generating different potentials by driving a capacitor by an oscillation signal, such as a step-up circuit (i.e., booster circuit) and a step-down circuit and more specifically, to a semiconductor device comprising a DRAM having such power source circuits.
2. Description of the Related Art
Generally, each of a plurality of memory cells that constitute a memory cell array in the DRAM includes one cell transistor for reading or writing data and one cell capacitor connected to the source of this cell transistor. The cell capacitor stores a charge depending on the logic “1” or “0” of the data written into the memory cell. A word line is connected to the gate of each cell transistor so as to supply a voltage necessary for bringing this cell transistor into an operating state (activated state).
When an N-channel transistor is used as the cell transistor inside each memory cell, a threshold voltage between the gate and the source of this N-channel transistor must be taken into consideration. In other words, when data is written or read by selecting a specific memory cell among a plurality of memory cells, a step-up voltage which is elevated by at least the threshold voltage between the gate and the source of the N-channel transistor is supplied from a word line to the gate of the N-channel transistor in order to reliably bring the cell transistor in this specific memory cell from the standby state to the activated state. Furthermore, in order to accomplish a high-speed operation of the DRAM, the cell transistor in the selected memory cell must be quickly returned from the activated state to the standby state after the data is written into, or read out, from the selected memory cell.
The operation that supplies a reset signal of a predetermined level from the word line to the cell transistor so as to return the cell transistor under the activated state to the standby state is generally referred to as the “reset operation” of the word line. A technology which sets the level of the reset signal (reset level, that is, reset potential) outputted from a word line driver circuit, to a potential of a negative voltage level (negative potential), but not to the ground potential, has been employed for this reset operation so as to minimize the leakage of the charges that are stored in the cell capacitor.
On the other hand, the integration density has become higher and higher in semiconductor memories (semiconductor memory devices) and scaling-down of the memory cell size has been made with a higher integration density. When the memory cell is scaled-down, a driving voltage must be lowered because the withstand voltage of the memory cell becomes low, and it becomes more difficult to insure a safe and reliable operation of the memory. Particularly in the case of the memories of such a type in which a capacitor is provided to each memory cell and the charge storing state and the charge non-storing storing state in the capacitor are allowed to correspond to the data values, as typified by the DRAM, the charges that are stored in the capacitor gradually drop due to the leakage current of the memory cell, and a re-write operation referred to as “refresh” must be carried periodically. When the memory cell is scaled down, the withstand voltage of the capacitor becomes low, so that a high voltage cannot be applied to the memory cell. In other words, the voltage of the power source must be lowered. The threshold voltage of the transistor must be also lowered with the decrease of the power source voltage, thereby inviting the problem that the leakage current when the cell transistor is not selected (sub-threshold leak) increases and the data retaining time becomes short. When the data retaining time becomes short, the cycle of the refresh operation must be shortened so as to cope with this short time, thereby inviting also the drop of performance of the DRAM such as the increase of the refresh current.
On the other hand, attempts have been made in recent years to reduce operating voltages of the semiconductor devices to improve the operation speed, to save power and to reduce noise. For instance, a driving voltage of 5 V has long been used for the semiconductor devices but recently, a 3.3 V voltage has been used and this voltage may become lower in the future. Nonetheless, such as a voltage alone is not sufficient to insure stability of the operation, and a higher voltage and a negative voltage becomes necessary. Therefore, a step-up power source circuit (i.e., boosting power source circuit) and a step-down power source circuit are provided inside the semiconductor device so as to generate the necessary voltages in the semiconductor device. The DRAM, in particular, has been developed by simplifying as much as possible the construction so as to attain a high integration density but recently, a high operation speed has become also an important object in addition to the high integration density.
In order to make the problem that is encountered when the reset potential of the word line is set to the negative potential during the reset operation of the memory cell in the DRAM, more easily understood, the construction and operations of DRAMs, etc., according to the prior art that have the function of executing the reset operation will be explained with reference to
FIGS. 1
to
5
of the accompanying drawings in the later-appearing “BRIEF DESCRIPTION OF THE DRAWINGS”.
FIG. 1
is a circuit diagram showing the construction of the first example of a semiconductor device having the function of setting a reset potential to a negative potential according to the prior art, and
FIG. 2
is a timing chart useful for explaining the operation of the prior art device shown in FIG.
1
. In this case, the drawings show the circuit construction for driving the word lines in the semiconductor device to simplify the explanation.
A word line driver
280
is shown disposed in
FIG. 1
for supplying a driving signal SWL of a predetermined voltage level to the word line connected to the gate of the cell transistor inside the memory cell. This word line driver
280
includes an inverter comprising a P-channel transistor
285
and an N-channel transistor
290
for outputting the driving signal SWL on the basis of a selection signal, and an N-channel transistor
295
for clamping the word line at a predetermined reset level (reset potential) on the basis of a reset control signal SWDX. The source of each N-channel transistor
290
,
295
is connected to a power source (negative power source) having a negative voltage Vnw
1
for resetting the word line. The N-channel transistor
295
becomes operative (ON) during the reset operation of the word line, and the output level of the driving signal SWL outputted from the word line driver circuit is
Eto Satoshi
Hasegawa Masatomo
Ishii Yuki
Kanou Hideki
Kawabata Kuninori
Arent Fox Kintner Plotkin & Kahn PLC
Tran Andrew Q.
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