Method for measuring fuse resistance in a fuse array

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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Reexamination Certificate

active

06541983

ABSTRACT:

This invention relates to a method for measuring fuse resistance in a fuse array; and particular the salicide poly fuse resistance in a fuse array, without a destructive de-layering process.
BACKGROUND OF THE INVENTION
At present, microprobing wafers or dies to measure a salicide poly fuse requires a de-layering process. This is a destructive process and slow at best. Once the top metal layer is removed and the fuses exposed, they can be measured by microprobes. This is a very tedious and slow process. At best, the resistance of only a few fuses can be measured in an hour. The de-layering and microprobing process is a very expensive procedure requiring a lot of engineering time and can be done only once per die, since it is destructive.
SUMMARY OF THE INVENTION
A simple electronics method for measuring the pre and post programming fuse resistance in a fuse array is incorporated into the design of the array. Non-destructive measuring the full resistance can be repeated many times, allowing fuse characterization under differing conditions. The process is extremely fast and is performed on the tester. All fuses in an array can be measured, and characterized. Statistical information can be extracted, and process, temperature and other conditions can be attributed.
Measuring the fuse resistance in a fuse array is the same process as blowing a fuse, but with a much lower current, for example 100 &mgr;A instead of 20 mA. The measured value or aggregate fuse resistance is the resistance of the wires, and the resistance of the devices used to switch the current. With a modification, it is possible to determine the voltage drop across the wires and switches, but not a fuse, giving more accurate measurement.
Broadly, the present invention comprises, positioning a fuse array, arranged in rows and columns, in a tester, the tester having an internal write source, means for controlling the write source, and a low current test source. The procedure includes disabling the internal write source, addressing the fuse array to select a fuse, applying the low current source to the fuse and measuring the voltage of this low current source. The resistance of the fuse is thus obtained. A suitable value for the low current source is between 100 &mgr;A and of 500 &mgr;A.
Using Spice simulation data a higher level of accuracy in resistance values is optionally obtained. To remove errors caused by wire and switch resistances, one fuse can be shorted to provide a datum value for wires and other non-fuse items.


REFERENCES:
patent: 5210699 (1993-05-01), Harrington
patent: 5635854 (1997-06-01), Shimanek et al.
patent: 5731733 (1998-03-01), Denham
patent: 5991220 (1999-11-01), Freyman et al.
patent: 6185705 (2001-02-01), Cutter et al.
patent: 6205050 (2001-03-01), Tamaki
patent: 6373762 (2002-04-01), Morgan

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