Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-04-06
2003-04-22
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S666000, C257S686000, C257S784000
Reexamination Certificate
active
06552437
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device, and more particularly to techniques which are effective when applied to a semiconductor device wherein two semiconductor chips are stacked and then encapsulated with an one resin body.
BACKGROUND ART
In order to enlarge the capacity of a storage circuit system, there has been proposed a stacked type semiconductor device wherein two semiconductor chips, in each of which a storage circuit subsystem is constructed, are stacked and then encapsulated with an one resin body. By way of example, a stacked type semiconductor device of LOC (Lead On Chip) structure is disclosed in the official gazette of Japanese Patent Laid-Open No. 58281/1995. Besides, a stacked type semiconductor device of tab structure is disclosed in the official gazette of Japanese Patent Laid-Open No. 302165/1992.
The stacked type semiconductor device of LOC structure is constructed having a first semiconductor chip and a second semiconductor chip in each of which a plurality of electrodes are formed on a circuit forming surface being the front surface (one principal surface) of front and rear surfaces (one principal surface and the other principal surface opposing to each other); a plurality of first leads which are bonded and fixed to the circuit forming surface of the first semiconductor chip through an insulating film, and which are electrically connected to the electrodes of this circuit forming surface through pieces of conductive wire; a plurality of second leads which are bonded and fixed to the circuit forming surface of the second semiconductor chip through an insulating film, and which are electrically connected to the electrodes of this circuit forming surface through pieces of conductive wire; and a resin body which encapsulates the first semiconductor chip, the second semiconductor chip, the inner portions of the first leads, the inner portions of the second leads, and the wire pieces. The first semiconductor chip and the second semiconductor chip are stacked to each other in a state where their circuit forming surfaces are held in opposition to each other. The first leads and the second leads are individually joined in a state where their connection portions are placed one over the other.
The stacked type semiconductor device of tab structure is constructed having a first semiconductor chip which is fixed to the front surface (one principal surface) of the front and rear surfaces (one principal surface and the other principal surface opposing to each other) of a tab (also termed “die pad”) through an adhesive layer; a second semiconductor chip which is fixed to the rear surface (the other principal surface) of the tab through an adhesive layer; a plurality of dedicated leads which are electrically connected to the electrodes of either of the first or second semiconductor chips through pieces of conductive wire; a plurality of common leads which are electrically connected to the electrodes of both of the first and second semiconductor chips through pieces of conductive wire; and a resin body which encapsulates the first semiconductor chip, the second semiconductor chip, the inner portions of the dedicated leads, the inner portions of the common leads, and the wire pieces. The electrodes of each of the first and second semiconductor chips are formed on the two longer latus sides of the circuit forming surface opposing to each other and along the respective longer latera thereof. The dedicated leads and the common leads are respectively arranged outside the two longer latera of each of the corresponding semiconductor chips.
Before developing a stacked type semiconductor device, the inventors envisaged problems stated below.
With the LOC structure, the semiconductor device is manufactured using two lead frames, and hence, the fabrication cost thereof becomes high. On the other hand, with the tab structure, the semiconductor device can be manufactured using a single lead frame. Since, however, the semiconductor chips of mirror inversion circuit patterns need to be employed, the fabrication cost of the semiconductor device becomes high even with the tab structure. More specifically, with the tab structure, the two semiconductor chips are respectively mounted on the front and rear surfaces of the tab with their rear surfaces facing each other. Therefore, in the case where the electrodes are formed on the sides of the two longer latera of each circuit forming surface opposing to each other, the electrodes of the lower semiconductor chip are reversed on the right and left sides to those of the upper semiconductor chip.
In this regard, the semiconductor chips of the mirror inversion circuit patterns are dispensed with by employing two semiconductor chips each of which is formed with electrodes on one latus side, and by mounting the two semiconductor chips on the front and rear surfaces of a tab so that one latus side of one semiconductor chip may be located on the opposite side of the other semiconductor chip to one latus side thereof. It is therefore possible to achieve curtailment in the fabrication cost of the semiconductor device of the tab structure.
With the tab structure, however, the thickness of the resin body enlarges, and it is difficult to construct the stacked type semiconductor device as a TSOP (Thin Small Outline Package) type whose resin body is 1.0~1.1 [mm] thick. More specifically, since the tab structure constructs the semiconductor device by mounting the semiconductor chips on the front and rear surfaces of the tab, the tab exists between the upper semiconductor chip and the lower semiconductor chip, and a distance from the circuit forming surface of the upper semiconductor chip to that of the lower semiconductor chip increases, so that the resin body thickens. Further, on account of the construction in which the semiconductor chips are mounted on the front and rear surfaces of the tab, two adhesive layers exist between the upper semiconductor chip and the lower semiconductor chip, and the distance from the circuit forming surface of the upper semiconductor chip to that of the lower semiconductor chip increases, so that the resin body thickens. The inventors study has revealed that the thickness of the resin body can be set at 1.0~1.1 [mm] or less by thinning each semiconductor chip down to 0.1725~0.2 [mm]. In such a case, however, the mechanical strength of the semiconductor chip lowers, and hence, drawbacks such as cracks and fractures are liable to occur in the semiconductor chip. The drawbacks often occur especially at the dicing step of fabrication for splitting a semiconductor wafer into a plurality of chips, and at the die bonding step of fabrication for mounting the semiconductor chips on the tab.
Besides, with the tab structure, inferior connections are liable to occur between the electrodes of the semiconductor chips and the wire pieces. More specifically, it is difficult to bring the tab into touch with a heat stage after the semiconductor chips have been mounted on the front and rear surfaces of the tab. Therefore, the heat of the heat stage is not effectively conducted, and the inferior connections between the electrodes of the semiconductor chips and the wire pieces are liable to occur.
An object of the present invention is to provide a technique capable of attaining the thinned construction of a semiconductor device wherein two semiconductor chips are stacked and then encapsulated with an one resin body.
Another object of the present invention is to provide a technique capable of heightening the available percentage of the products of the thinned semiconductor device.
The above and other objects and novel features of the present invention will become apparent from the description of this specification when read in conjunction with the accompanying drawings.
DISCLOSURE OF THE INVENTION
Typical aspects of performance out of the present invention disclosed in this application are briefly summarized as follows:
(1) A semiconductor device comprising a resin body; a first semico
Higashino Tomoko
Masuda Masachika
Nishita Takafumi
Ohno Hiroshi
Sugiyama Michiaki
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Nelms David
Nguyen Dao H.
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