Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-11-10
2003-09-16
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S756010, C324S765010, C324S073100
Reexamination Certificate
active
06621283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device mounted on a board or the like having the function of carrying out a contact test at a relatively low cost to check a state of a contact of terminals of the semiconductor device, a method of testing the semiconductor device and a semiconductor integrated circuit.
In the process of mounting a semiconductor device consisting of a memory device such as a DRAM (dynamic random access memory) on a board or the like, it is important to confirm whether or not terminals of the memory device and terminals of the board are assuredly connected with each other by means of solder or the like, i.e., to carry out a contact check of the terminals of the memory device after the memory device is mounted on the board or the like.
Generally, a memory device such as a DRAM is packaged into a thin package of a surface mount type such as a TSOP (thin small outline package). The conditions of soldering of the terminals can be visually checked with these packages being mounted on the board, and therefore the contact check of the terminals of the memory device after the memory device is mounted on the board or the like, has thus far been carried out visually.
With a reduction of the size of a personal computer year by year, however, the packaging area of the memory device tends to decrease gradually. To meet the tendency toward the decrease in the packaging area of the memory device, in recent years a package having a smaller packaging area such as a CSP (chip size package) having substantially the same outer dimensions as a chip (1 cm square) has been fabricated. This type of package has a number of electrodes arranged in a matrix in the two-dimensional directions on the bottom thereof. Once the above type of package is mounted on the board, therefore, it is no longer easy to visually check the state of the contact of the terminals of the memory device.
2. Description of the Related Art
As described above, after packaging a memory device such as a DRAM into a package having a smaller packaging area (e.g., CSP) and mounting this particular package on a board, it is difficult to visually check the state of the contact of the terminals of the memory device. It is therefore necessary to carry out the contact check by actually activating the DRAM or the like. In the conventional method, a test circuit is prepared in which the contact check can be carried out by accurately setting the timing of associated signals. This method, however, unavoidably leads to the disadvantage of a relatively high cost for the contact check.
To cope with this disadvantage, a logic device such as a gate array is fabricated so as to include a simple test circuit therein for carrying out the contact check of the terminals by means of a boundary scan method which is usually practiced in the field of semiconductor device industry. The test circuit of this type requires no complicated setting of the timing of associated signals, and therefore the contact check of the terminals of the logic device can be easily carried out.
When carrying out the contact check with the above boundary scan method, or the like, described above, however, at least one additional terminal is usually required for activating the test circuit for contact check. In general, the logic device has many terminals (200 to 256 pins, for example) and is fabricated as a custom-made product based on a user's specification, and therefore at least one dedicated terminal can be easily provided for activating the test circuit for contact check.
However, in the case in which the test circuit for contact check of the logic device described above is to be applied to a memory device such as a DRAM, the following problems occur when activating the test circuit.
The memory device is often fabricated as a general-purpose product and usually designed with the minimum required number of terminals. For the memory device such as the DRAM, therefore it is difficult to provide any additional terminal that may be dedicated to the test circuit.
Further, in view of the need for carrying out the test for contact check with the memory device being mounted on the board, it is difficult to activate the test circuit by applying a specific voltage to a specific terminal.
In carrying out the contact check of the terminals of a semiconductor device consisting of a memory device such as a DRAM, therefore, a test circuit is required which can be activated by setting the timing of associated signals simply within the voltage range normally applied and also by utilizing existing terminals. On the other hand, such a test circuit must not be easily activated in the conditions of normal operations of the memory device, other than the conditions of the test for the terminal contact check, in order to prevent the test circuit from having an influence on the normal operations of the memory device.
SUMMARY OF THE INVENTION
The present invention has been developed in view of the above-mentioned problems, and the object thereof is to provide a semiconductor device including a test circuit which can be activated with a simple activation sequence without any dedicated terminal and, which is not easily activated in the condition of normal operations, a method of testing the terminals by utilizing the above test circuit or the like, and a semiconductor integrated circuit having the above test circuit.
In order to solve the problems mentioned above, according to the present invention, there is provided a semiconductor device comprising a terminal test circuit for testing the state of the contact of an external terminal; and a test mode control circuit unit for outputting a signal indicating a first operation mode when a power supply voltage is applied thereto, for outputting a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal in the first operation mode, and for outputting a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes.
According to another aspect of the present invention, there is provided a method of testing the terminals of a semiconductor device, comprising the steps of:
carrying out a first test by applying a power supply voltage to the power supply terminal of the semiconductor device and supplying a chip select signal of an active level to a chip select terminal in the semiconductor device thereby to check the state of the contact of the chip select terminal and the power supply terminal;
carrying out a second test by returning the chip select signal to an inactive level and then restoring the chip select signal to an active level, and activating a test circuit for checking the state of the contact any input terminals other than the chip select terminal thereby to check the state of the contact of the input terminals; and
carrying out a third test by returning the chip select signal to an inactive level and then restoring the chip select signal to an active level, and activating the test circuit for checking the state of the contact of at least a data input/output terminal thereby to check the state of the contact of the data input/output terminal.
According to still another aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first external terminal and a second external terminal each connected to an internal circuit; a test mode control circuit unit which is activated when a power supply voltage is applied thereto to output a test mode signal in response to a control signal applied to the first external terminal, and is deactivated when the logic level of the control signal changes the number of times equal to a predetermined value; and a terminal test circuit unit connected to the second external terminal to determine the state of the contact of the second external terminal in response to the test mode signal.
More specifically, in the semiconductor device and the testing method ac
Fujii Yasuhiro
Hatakeyama Atsushi
Kawasaki Ken'ichi
Matsuzaki Yasurou
Nakano Masao
Arent Fox Kintner & Plotkin & Kahn, PLLC
Cuneo Kamand
Fujitsu Limited
Patel Paresh
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