Tester accuracy using multiple passes

Details Tester accuracy using multiple passes Tester accuracy using multiple passes

2001-05-08

2003-01-14

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C324S763010, C324S073100, C714S726000, C714S729000

Reexamination Certificate

active

06507209

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for device testing generally and, more particularly, to device testing to an effective accuracy finer than the test equipment accuracy.
BACKGROUND OF THE INVENTION
Accuracy of semiconductor device testing is limited by an accuracy of the test equipment performing the test. For example, a test that determines if a propagation delay through a device meets or exceeds a 10 nanosecond (ns) requirement necessitates test equipment that can measure time intervals shorter than 10 ns. The test equipment commonly has an accuracy of one to two orders of magnitudes finer than the parameter being tested. For example, a 250 picosecond (ps) accuracy is suitable for measuring the 10 ns time interval in practical test situations.
The finite test equipment resolution results in uncertainties in the actual measurements. To guarantee that the device meets the 10 ns performance requirement, the actual device performance must exceed the requirement by the accuracy of the test equipment. In other words, the test equipment accuracy creates a guardband adjacent to the performance requirement that the device must exceed in order to pass the test. Consequently, a borderline device that meets the performance requirement but falls within the guardband fails the test due to errors induced by the test equipment. The guardband can be reduced by using more accurate and thus more expensive test equipment.
SUMMARY OF THE INVENTION
The present invention concerns a test circuit generally comprising a tester connected to a socket for holding a device under test. The device may be configured to have (i) a first function and (ii) a final function. The tester may be configured to (i) stimulate the first function with a test signal to present a first output signal, (ii) stimulate the final function with the first output signal to present a final output signal, (iii) measure a result between the test signal and the final output signal, and (iv) allocate the result between the first function and the final function to disperse a measurement error in the result.
The objects, features and advantages of the present invention include providing a method and/or architecture for device testing to an effective accuracy finer than the test equipment accuracy that may (i) reduce overall device testing time, (ii) effectively reduce test equipment induced measurement errors, and/or (iii) result in a higher device pass rate.


REFERENCES:
patent: 6144262 (2000-11-01), Kingsley
patent: 6158032 (2000-12-01), Currier et al.

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