Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1997-05-02
2003-01-21
Yoo, Do Hyun (Department: 2511)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185090, C365S185220, C365S201000
Reexamination Certificate
active
06510083
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of memories. More particularly, this invention relates to an apparatus and a method for allowing data update in an electrically erasable and programmable memory without prior erasure of the memory.
BACKGROUND OF THE INVENTION
One type of prior art nonvolatile memory is a flash Erasable and electrically Programmable Read-Only Memory (“flash EPROM”). A typical flash EPROM has the same array configuration as a standard Electrically Programmable Read-Only Memory (“EPROM”) and can be programmed in similar fashion as EPROM. Once programmed, the entire contents of the flash EPROM can be erased by electrical erasure in one relatively rapid operation. A high erasing voltage is made available to the sources of all the cells in the flash EPROM or in one block of the flash EPROM simultaneously. This results in a full array erasure or block erasure. The flash EPROM or the erased block of the flash EPROM may then be reprogrammed with new data.
Flash EPROMs differ from conventional Electrically Erasable Programmable Read Only Memory (“EEPROMs”) with respect to erasure. Conventional EEPROMs typically use a select transistor for individual cell erasure control. Flash EPROMs, on the other hand, typically achieve much higher density with single transistor cells. As described above, during the erasure of the flash EPROM, a high voltage is supplied to the sources of all memory cells in a memory array or a block of the memory array simultaneously. This results in a full array erasure or block erasure.
For a prior art single bit flash EPROM, a logical “one” means that few, if any, electrons are stored on a floating gate associated with a bit cell. A logical “zero” means that many electrons are stored on the floating gate associated with the bit cell. Erasure of the flash EPROM causes a logical one to be stored in each bit cell. Each single bit cell of the flash EPROM cannot be overwritten from a logical zero to a logical one without a prior erasure. Each single bit cell of that flash EPROM can, however, be written from a logical one to a logical zero, given that this entails simply adding electrons to a floating gate that contains the intrinsic number of electrons associated with the erased state.
One disadvantage of the flash EPROM, however, is that each single bit cell cannot be overwritten from the logical zero to the logical one without a prior erasure. Another disadvantage of the flash EPROM is that it must be erased—i.e., reset to the logical one state—in large blocks or in a manner that erases the entire device.
Another disadvantage of the flash EPROM is that there is a finite limit on the number of erase and write cycles for the flash EPROM before the flash EPROM will fail.
The limitations with respect to overwriting and erasure associated with the flash EPROMs have, in certain instances, limited the usefulness of the flash EPROMs.
SUMMARY AND OBJECTS OF THE INVENTION
One of the features of the present invention is to allow an electrically erasable and programmable memory to emulate a random access memory (RAM).
Another feature of the present invention is to provide an arrangement that allows a block-erasable nonvolatile memory to have byte alterability feature.
A further feature of the present invention is to provide apparatus and a method for updating data stored in an electrically erasable and programmable nonvolatile memory without a prior erasure of the memory.
Described hereinafter is a processor-implemented method for updating a datum stored in a nonvolatile memory, bits of which cannot be overwritten from a first logical state to a second logical state without a prior erasure of the memory. The method includes the step of accessing a first storage location in the memory that stores a first version of the datum. A status field of the first storage location is checked to determine whether the first version of the datum has been superseded. If the status field of the first storage location indicates that the first version of the datum has not been superseded, then a most recent version of the datum is stored in a second storage location of the memory. An address of the second storage location is written into a next location address field of the first storage location. The status field of the first storage location is then written to indicate that the first version of the datum has been superseded such that the datum is updated without the prior erasure of the memory.
An apparatus for storing a datum is also described that includes a processor and a nonvolatile memory having a first and a second processor-allocated storage location, each including memory cells that cannot be overwritten from a first logical state to a second logical state without a prior erasure of the memory. The first processor-allocated storage location further includes a data field that stores a version of the datum, a status field indicating whether the version of the datum stored in the data field has been superseded by an updated version of the datum stored in the second storage location of the memory, and a next pointer field that stores an address of the second processor-allocated storage location that stores the updated version of the datum such that the datum is updated in the memory without the prior erasure of the memory.
REFERENCES:
patent: 5197034 (1993-03-01), Fandrich et al.
patent: 5245572 (1993-09-01), Kosonocky et al.
patent: 5379256 (1995-01-01), Tanaka et al.
patent: 5424991 (1995-06-01), Hu
patent: 5434825 (1995-07-01), Harari
Hazen Peter K.
See Deborah L.
Blakely & Sokoloff, Taylor & Zafman
Intel Corporation
Yoo Do Hyun
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