Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-03-31
2003-05-13
Oda, Christine (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06563330
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 11-233109.
BACKGROUND OF THE INVENTION
The present invention relates to a probe card for simultaneous testing. More particularly, the present invention relates to a probe card for a wafer to test a plurality of chips and chip size to packages (hereinafter referred to as CSP) formed on the wafer and a method of testing a semiconductor device such as the wafer level CSP or the like.
In order to form a semiconductor device sealed by resin having such a shape that is as close as possible to a semiconductor chip (hereinafter referred to as chip), applicant suggests a new semiconductor package having the structure that external output terminals formed by projecting electrodes are provided on the chip. At least the side surface of the projecting electrode is sealed by resin in the wafer condition and thereafter chips are cut into individual chips (refer to Japanese Published Unexamined Patent Application No. HEI 10-79362, and U.S. patent application Ser. No. 09/029,608).
More effective testing of the semiconductor device can be realized by conducting the testing when the CSPs are in the wafer condition, rather than conducting testing for individual CSPs cut from the wafer. The same can be said for testing wafers on which a plurality of ordinary chips are formed. The present invention relates to a probe card for testing each of a plurality of chips and CSPs in the wafer condition and a method of testing the wafer having a plurality of semiconductor devices.
FIGS. 1
to
4
are diagrams illustrating an example of a CSP of the related art.
FIG. 1
is a cross-sectional view, while
FIG. 2
illustrates the condition before CSPs like that of
FIG. 1
were cut into individual pieces and
FIG. 3
is a plan view of FIG.
2
.
In the CSP illustrated in
FIG. 1
, an area other than aluminum pad
4
on a chip
1
is covered with a silicon nitride film
2
and a polyimide layer
3
is further formed thereon. An aluminum electrode pad
4
formed on the chip
1
has problems in that a probe cannot make contact with it at the time of testing because its interval is too narrow in the non-modified arrangement and the pad cannot be mounted on the mounting substrate at the time of mounting. Therefore, a re-distribution trace
5
is formed on the polyimide layer
3
, connecting the aluminum pad
4
to a copper projecting electrode
6
at an appropriate position on the chip, thereby widening the interval of the aluminum pads
4
. For the mounting on a printed board, solder ball
8
is formed on the copper projecting electrode
6
via a barrier metal layer
7
.
When manufacturing the CSP of
FIG. 1
, after the copper projecting electrode
6
is formed on the wafer, a resin layer
9
is formed t
6
seal at least the side surface of the copper projecting electrode
6
. Thereafter, solder balls
8
are formed and then the CSPs on the wafer are cut into individual pieces along the dicing line
12
as illustrated in FIG.
2
.
However, at the time of testing the CSP, since testing efficiency is reduced after the solder balls
8
are divided into individual pieces, it is strongly desired to conduct the testing of the CSPs while they are still in the wafer condition before the cutting as illustrated in FIG.
3
.
FIG. 3
illustrates the condition that the CSP is formed in the wafer condition and the wafer
11
is held by a tape
10
. When a probe formed of an ordinary stylus is applied to the electrode pad (not illustrated) of each chip under this condition, a probe having a stylus corresponding to the interval of the narrow pad must be prepared, resulting in increased cost.
As a method not using a probe formed of a stylus, there is provided a method using anisotropic conductive rubber, as illustrated in FIG.
4
. In this method, a flexible substrate
42
is provided on the anisotropic conductive rubber
41
, which is pressed into contact with the wafer to be tested, and a signal on the electrode on the wafer is electrically guided to a multi-layer substrate
43
.
However, the method using the anisotropic conductive rubber has the following problems. Since the anisotropic conductive rubber is used, the wiring cannot be led to a multi-layer substrate so as to widen the pitch of electrodes on the wafer. Therefore, wiring must be laid on the multi-layer substrate under the electrode pitch of the wafer without change in the pitch. Moreover, fluctuation of flatness which may be absorbed by the anisotropic conductive rubber is ranged from 25 to 50 &mgr;m and therefore an expensive ceramic substrate having excellent flatness is used as the multi-layer substrate. When the electrode pitch on the wafer is realized by the ceramics multi-layer substrate, through hole must be bored within a narrow pitch. Therefore, when a ceramics substrate is used for the multi-layer substrate, a probe card becomes expensive because such a substrate is originally expensive and processing cost is also high.
Here, when a low cost printed circuit board formed of glass epoxy or the like is used for the multi-layer substrate, strain of about 100 &mgr;m is generated at the contact area between the anisotropic conductive rubber and multi-layer substrate, which is not preferable for contact area stability.
Moreover, the anisotropic conductive rubber cannot cover the resolution when the electrode pitch of wafer becomes 100 &mgr;m or less.
Moreover, since the probe card is exposed to high temperatures in the burn-in test, the anisotropic conductive rubber can bear only 100 times of use, so its durability is also a problem.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a probe card and a method of testing a wafer having formed a plurality of semiconductor devices which always assure good contact with each chip and electrode pad of CSP without using multi-layer ceramics substrate and anisotropic conductive rubber at the time of testing chips and CSPs in the wafer condition.
It is a further object of the present invention to cover narrow electrode pitches.
It is a further object of the present invention to assure excellent durability under high temperatures.
Objects of the invention are achieved by a probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board. An electrode pitch between connecting terminals is greater than an electrode pitch between contact electrodes.
Objects of the invention are also achieved by a method for forming a probe card, including the steps of forming contact electrodes aligned opposite from corresponding electrodes on the plurality of semiconductor devices; expanding an electrode pitch of the contact electrodes with first wirings; bending each of the first wirings to form a level transitioning portion extending from a level of the contact electrodes to a multi-layer substrate at a lower level; bonding connecting terminals at an end of the level transitioning portion of each of the first wirings to internal terminals on the multi-layer substrate; connecting the internal terminals on the multi-layer substrate to external terminals at a periphery of the multi-layer substrate with second wirings; and placing the
Honda Toshiyuki
Kawahara Toshimi
Koizumi Daisuke
Konno Yoshito
Maruyama Shigeyuki
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Kerveros James
Oda Christine
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