Semiconductor integrated circuit device having internal...

Details Semiconductor integrated circuit device having internal... Semiconductor integrated circuit device having internal...

2001-10-17

2003-03-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Powering

C365S189090

Reexamination Certificate

active

06529437

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices. More specifically, the invention relates to a semiconductor integrated circuit device including a circuit for generating an internal supply voltage to be provided to a sense amplifier.
2. Description of the Background Art
The operating supply voltage of recent semiconductor integrated circuit devices has remarkably been decreasing. As an example, an array operating potential Vdds is now considered that is an operating supply potential of a sense amplifier and is equal to H data written into a memory cell of a dynamic random access memory (DRAM).
In general, array operating potential Vdds is generated by internally decreasing an external supply potential ext.Vdd. Array operating potential Vdds is determined from the reliability of an insulating film which constitutes a memory cell capacitor. The recent reduction in the design rule leads to reduction in the thickness of the insulating film. Then, decrease of a potential difference applied to the film is required. Accordingly, there arises a need for decrease of array operating potential Vdds because of the reduced thickness of the insulating film.
However, in terms of an array operating margin, the lowered level of array operating potential Vdds is disadvantageous.
FIG. 7
is a circuit diagram showing a partial structure of a memory cell array in a DRAM.
Referring to
FIG. 7
, the memory cell array in the DRAM includes a sense amplifier
30
, a bit line equalize circuit
20
, and a memory cell
10
.
Sense amplifier
30
includes P channel MOS transistors P
1
and P
2
and N channel MOS transistors N
1
and N
2
.
P channel MOS transistor P
1
is connected between a node A
3
and a P channel MOS transistor P
3
, and P channel MOS transistor P
2
is connected between a node A
4
and P channel MOS transistor P
3
.
N channel MOS transistor N
1
is connected between node A
3
and an N channel MOS transistor N
3
, and N channel MOS transistor N
2
is connected between node A
4
and N channel MOS transistor N
3
.
P channel MOS transistor P
1
and N channel MOS transistor N
1
have respective gates connected to node A
4
and P channel MOS transistor P
2
and N channel MOS transistor N
2
have respective gates connected to node A
3
. Node A
3
is connected to a bit line BL and node A
4
is connected to a bit line ZBL.
The source of P channel MOS transistor P
3
is connected to an internal supply voltage generating circuit (VDC)
40
via a sense power supply line VSH (interconnect resistance R
1
) and the gate thereof is connected to a node ZSOP.
N channel MOS transistor N
3
is grounded via a node VSL (interconnect resistance R
2
).
Bit line equalize circuit
20
includes an N channel MOS transistor N
4
connected between bit lines BL and ZBL and N channel MOS transistors N
5
and N
6
connected in series between bit lines BL and ZBL. Respective gates of N channel MOS transistors N
4
to N
6
are connected to a node A
2
. The connecting point of N channel MOS transistors N
5
and N
6
is connected to a node A
1
. Node A
2
receives a bit line equalize signal BLEQ and node A
1
receives a bit line potential Vbl. Bit line equalize circuit
20
equalizes the potentials on bit lines BL and ZBL to bit line potential Vbl in response to rising of bit line equalize signal BLEQ to H level of an activation level. Bit line potential Vbl is equal to half of array operating potential, Vdds/2.
Memory cell
10
includes an N channel MOS transistor N
7
for access and a capacitor C
1
for information storage. The gate of N channel MOS transistor N
7
in memory cell
10
is connected to a word line WL of a corresponding row. N channel MOS transistor N
7
is connected between bit line BL and one electrode (storage node SN) of capacitor C
1
. The other electrode of capacitor C
1
receives a cell plate potential Vcp. Word line WL activates memory cell
10
. Paired bit lines BL and ZBL supply/receive a data signal to and from a selected memory cell.
When memory cell
10
holds H data, a data reading operation is performed as described below.
FIG. 8
is a timing chart showing an operation of sense amplifier
30
in FIG.
7
.
Referring to
FIG. 8
, in a precharge state prior to time T
1
, bit line equalize signal BLEQ in bit line equalize circuit
20
has H level and accordingly N channel MOS transistors N
4
to N
6
in bit line equalize circuit
20
are turned on. Then, before time T
1
, respective potentials on paired bit lines BL and ZBL are precharged to bit line potential Vbl which is the intermediate potential between array operating potential Vdds of an H data potential and ground potential GND of an L data potential.
At time T
1
, word line WL is activated to H level so that N channel MOS transistor N
7
in memory cell
10
is turned on and the H data held in memory cell
10
is transmitted to bit line BL. Consequently, the potential on bit line BL increases from bit line potential Vbl by a minute potential dV. The potential on bit line ZBL stays at bit line potential Vbl and thus a potential difference occurs between paired bit lines BL and ZBL.
At time T
2
, sense amplifier activation signals ZS
0
P and S
0
N become respectively to L and H levels so that P channel MOS transistor P
3
and N channel MOS transistor N
3
are turned on and sense amplifier
30
is activated. Then, the potential difference between paired bit lines BL and ZBL is amplified and bit line BL and storage node SN of memory cell
10
are raised to array operating potential Vdds which is the potential of H data. Moreover, the potential on bit line ZBL is lowered from bit line potential Vbl to ground potential GND.
It is supposed here that P channel MOS transistors P
1
and P
2
constituting sense amplifier
30
both have a threshold potential Vthp and N channel MOS transistors N
1
and N
2
constituting sense amplifier
30
both have a threshold potential Vthn. In order for sense amplifier
30
to start its operation at time T
2
, it is necessary that gate-source potential Vgs of P channel MOS transistors P
1
and P
2
should be higher than potential Vthp and gate-source potential Vgs of N channel MOS transistors N
1
and N
2
should be higher than potential Vthp. Gate-source potential Vgs can be represented by the following equation when minute potential dV is ignored.
Vgs=Vbl=Vdds
/2
Then, for operation of sense amplifier
30
, array operating potential Vdds should have the relation below.
Vdds
>max(2
×Vthn
, 2
×|Vthp
|)  (1)
Accordingly, array operating potential Vdds on sense power supply line VSH should be any potential which satisfies relation (1).
Further, an initial operating speed of sense amplifier
30
is determined by respective differences, Vgs−|Vthp| and Vgs−Vthn, between gate-source potential Vgs of respective MOS transistors in sense amplifier
30
and threshold voltages Vthp and Vthn of respective MOS transistors.
In view of this, if threshold voltages Vthp and Vthn of respective transistors vary due to change in a manufacturing process, a decreased array operating potential Vdds results in an insufficient operation margin of sense amplifier
30
. In addition, if the decreased array operating potential Vdds makes it impossible to obtain an enough Vgs−|Vthp| or Vgs−Vthn, sense amplifier
30
requires an extended operating time.
After time T
2
in
FIG. 8
, the potentials on sense power supply line VSH and node VSL during operation of sense amplifier
30
change transitionally depending on the interconnect resistances of sense power supply line VSH and node VSL, response rate of VDC circuit
40
and the like. In other words, the potential on sense power supply line VSH decreases to the lowest level at time T
3
and the potential on node VSL increases to the highest level at time T
3
. Such a variation of the potentials on sense power supply line VSH and node VSL during the sensing operation considerably deteriorates the operating speed of

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