Static information storage and retrieval – Powering
Reexamination Certificate
2002-05-30
2003-09-02
Riley, Shawn (Department: 2838)
Static information storage and retrieval
Powering
C365S227000, C365S189110
Reexamination Certificate
active
06614707
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power supply circuit and more particularly, to a power supply circuit converting an external power supply potential into an internal power supply potential to supply the internal power supply potential to a load and a configuration of a semiconductor memory device with the same.
2. Description of the Background Art
A withstand voltage of an internal circuit of a semiconductor device has been reduced through progress in microfabrication according to increased requirement for a larger capacity of a semiconductor memory device. In order to cope with such a situation, in a semiconductor memory device, an external power supply potential, for example, of 5 V or 3.3 V is stepped down to a proper internal power supply potential (for example, 2.5 V, 2.0V or the like) by a power supply circuit provided internally (hereinafter also referred to as an internal power supply circuit). Such an internal power supply circuit is referred to as a voltage down converter (VDC) as well.
When an internal power supply potential generated by a power supply circuit is reduced to a value lower than a prescribed level, a group of internal circuits of a semiconductor memory device has a risk that neither of the internal circuits can perform a prescribed operation at a prescribed speed since the internal power supply potential is used by each of the internal circuits in the semiconductor memory device. On the other hand, when the internal power supply potential rises and exceeds a prescribed level, there arises a risk that not only does power consumption increase, but transistors miniaturized due to progress to higher integration are also electrically broken. Hence, the power supply circuit has to control a level of the internal power supply potential in a stable manner such that fluctuations in the internal power supply potential are confined within a prescribed range determined by specifications of the semiconductor memory device.
FIG. 31
is a circuit diagram representing a configuration of a prior art internal power supply circuit
500
having a typical configuration of VDC.
The internal power supply circuit
500
is a circuit for receiving an external power supply potential ext.Vdd from an external power supply line
510
to hold an internal power supply potential int.Vdd supplied to a load
550
at a reference voltage Vref.
Referring to
FIG. 31
, the internal power supply circuit
500
includes: an external power supply line
510
supplying an external power supply potential ext.Vdd; an internal power supply line
520
supplying an internal power supply potential int.Vdd; a potential difference amplifying circuit
530
amplifying and outputting a potential difference between the internal power supply potential int.Vdd and a reference potential Vref; a current supply transistor QD
1
supplying a current Isup to the internal power supply line
520
from the external power supply line
510
according to an output of the potential difference amplifying circuit
530
; and an stabilization capacitance
545
for suppressing fluctuations in potential level of the internal power supply line
520
. The load
550
receives supply of the internal power supply potential int.Vdd from the internal power supply line
520
and consumes a load current Iload.
The potential difference amplifying circuit
530
includes P type MOS transistors QP
1
and QP
2
, and N type MOS transistors QN
1
, QN
2
and QN
3
constituting a current mirror amplifier coupled between the external power supply line
510
and a ground line
540
. The reference voltage Vref and the internal power supply potential int.Vdd are inputted to the respective gates of the transistors QN
1
and QN
2
. The gates of the transistors QP
1
and QP
2
are coupled to a node Np. The transistor QN
3
supplies an operating current of the current mirror amplifier in response to activation of a control signal ACT.
The transistors QP
1
, QP
2
, QN
1
, QN
2
and QN
3
are designed in such a manner to operate in respective saturation regions and thereby, the potential difference amplifying circuit
530
amplifies differentially a gate potential difference of the transistors QN
1
and QN
2
such that the gate potential difference is reflected on a potential level of a node Nd.
When an internal power supply potential int.Vdd is lower than the reference potential Vref, a potential level of the node Nd is shifted to the ground potential Vss side and in response to the shift, the current supply transistor QD
1
supplies a current to the internal power supply line
520
from the external power supply line
510
. On the other hand, when an internal power supply potential int.Vdd rises beyond the reference potential Vref, a potential level of the node Nd is shifted to the external power supply potential ext.Vdd side; therefore, the current supply transistor QD
1
is turned off to stop current supply to the internal power supply line
520
. With such operations, the internal power supply circuit
500
compensates for fluctuations in the internal power supply potential int.Vdd to hold the internal power supply potential int.Vdd at a level of the reference potential Vref.
However, various patterns exist in current consumed by the load
550
receiving supply of an internal power supply potential int.Vdd from the internal power supply line
520
.
FIG. 32
is a timing chart representing operation of the internal power supply circuit corresponding to an example pattern of current consumption of the load
550
. In
FIG. 32
, shown is a current waveform of a load consuming a small amount of current continuously. As a typical example load having such as current consumption pattern, there can be named a peripheral circuit such as a signal buffer used in a DRAM (Dynamic Random Access Memory).
Referring to
FIG. 32
, the internal power supply circuit is active during a period when a control signal ACT is active. Since a load current Iload of the load
550
is continuously consumed, no much difference occurs between an instant value I
1
and an average value of the load current. Hence, a drop &Dgr;V
1
in level of an internal power supply potential int.Vdd can be suppressed to a comparatively low level by the action of the stabilization capacitance
545
.
Therefore, the current supply transistor QD
1
can follow gradual reduction in potential level occurring on the internal power supply line
520
by the action of the current Isup controlled by the potential difference amplifying circuit
530
and supplied to the internal power supply line
520
. As a result, the internal power supply potential int.Vdd never decreases lower than the reference potential by a great difference. Consequently, there is a low possibility to produce a problem such as malfunction in the internal circuitry, which is a load receiving supply of the internal power supply potential.
FIG. 33
is a timing chart representing operation of an internal power supply circuit corresponding to another example pattern of load current consumption. In
FIG. 33
, shown is a current waveform of a load consuming a load current Iload with a large amplitude, supplied intermittently. As a typical example of a load with such a current consumption pattern, there can be named a sense amplifier used in a DRAM.
In a case of
FIG. 33
as well, the internal power supply circuit is active during a period when a control signal ACT is active. However, in a case of a load current with a large amount, supplied intermittently, a large difference occurs between an instant value I
2
and an average value of a load current; therefore, an internal power supply potential int.Vdd cannot be sufficiently held by the action of a supply current Isup of the current supply transistor QD
1
controlled by the potential difference amplifying circuit
530
. As a result, a drop &Dgr;V
2
of the internal power supply potential is rendered larger. With a large value in the drop &Dgr;V
2
, there arises a possibility to deteriorate operation of an internal circuit, which is a load re
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