Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-10-11
2003-04-22
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S581000, C361S111000
Reexamination Certificate
active
06552583
ABSTRACT:
BACKGROUND OF INVENTION
This invention relates to integrated circuits, and more particularly to input-protection and electro-static-discharges (ESD) protection circuits.
Higher-density integrated circuits (IC's) are made possible by advances in semiconductor manufacturing, especially by reducing transistor size. However, smaller transistors are more sensitive to damage from external shocks, such as electro-static-discharges (ESD). Thinner gate oxides can be shorted, and substrate junctions melted by relatively small currents applied to the tiny devices. Static charges from a person or machinery can produce such damaging currents.
The input/output (I/O) pads of a semiconductor chip almost always have special protection circuits designed to block such ESD currents from reaching and damaging interior transistors. A wide variety of ESD-protection circuits and devices are in use today. Yet the design of such ESD-protection circuits remains as much of an art as a science.
FIG. 1
is a prior-art ESD-protection circuit. Core circuitry on the IC controls pre-driver
14
, which drives the gates of p-channel driver transistor
22
and n-channel driver transistor
24
. Driver transistors
22
,
24
have their drains connected to I/O pad
10
, and drive signals off-chip.
I/O pad
10
can sometimes operate as an input rather than an output. An external signal applied to I/O pad
10
can drive internal circuitry in the core by passing through series resistor
20
and input buffer
12
. I/O protection circuit
18
includes series resistor
20
and n-channel grounded-gate transistor
23
. When an ESD pulse is applied to I/O pad
10
, series resistor
20
can dissipate some of the energy and reduce the voltage on the input of input buffer
12
. Grounded-gate transistor
23
can turn on to shunt the ESD pulse to ground, either by normal channel conduction for a negative ESD pulse, or by drain-to-source breakdown (punch-through). A thicker field-oxide may be used for the gate oxide of grounded-gate transistor
23
rather than the more damage-prone thin gate oxide.
A second protection circuit is added for further protection. ESD protection circuit
16
is placed between I/O pad
10
and series resistor
20
. An R-C network is attached to the gate of n-channel ESD transistor
26
. When an ESD pulse occurs, the rapid rise in voltage is coupled from I/O pad
10
to the gate of n-channel ESD transistor
26
by capacitor
30
. The rise in voltage turns on n-channel ESD transistor
26
, allowing it to shunt current from I/O pad
10
to ground. This can keep the voltage at the drains of driver transistors
22
,
24
below their breakdown voltage, protecting them as well as protecting input buffer
12
.
Resistor
28
keeps the gate of n-channel ESD transistor
26
at ground during normal operation. However, during normal operation high-speed signals may couple through capacitor
30
to the gate of n-channel ESD transistor
26
, possibly even turning it on, or allowing sub-threshold conduction to occur if not fully turned on. This can degrade input signal quality and even cause false signal reception.
Capacitance is also added to the input, due to the capacitance of capacitor
30
. Often large device sizes are needed for protection circuits to handle the large ESD currents. The large device sizes can increase die size and IC cost. The additional capacitance can limit higher-frequency operation. Newer, low-voltage processes can have lower threshold voltages, and thus n-channel ESD transistor
26
may more easily turn on as devices are scaled down. Such unwanted turning on of ESD transistors during normal input switching can hinder IC operation.
What is desired is an ESD-protection circuit for high-frequency and low-voltage circuits. A lower-cost, reduced-die-area ESD structure is desirable, one that has minimal additional capacitance and does not accidentally turn on during normal input switching for normal operation of the IC.
REFERENCES:
patent: 4678950 (1987-07-01), Mitake
patent: 4855620 (1989-08-01), Duvvury et al.
patent: 5208719 (1993-05-01), Wei
patent: 5287241 (1994-02-01), Puar
patent: 5442217 (1995-08-01), Mimoto
patent: 5537067 (1996-07-01), Carvajal et al.
patent: 5631793 (1997-05-01), Ker et al.
patent: 5686751 (1997-11-01), Wu
patent: 5710682 (1998-01-01), Arya et al.
patent: 5729419 (1998-03-01), Lien
patent: 5959488 (1999-09-01), Lin et al.
patent: 5982217 (1999-11-01), Chen et al.
patent: 5986867 (1999-11-01), Duvvury et al.
patent: 5990723 (1999-11-01), Tanase
patent: 6064556 (2000-05-01), Ravanelli
patent: 6118323 (2000-09-01), Chaine et al.
patent: 6118640 (2000-09-01), Kwong
patent: 6249410 (2001-06-01), Ker et al.
Auvinen Stuart T.
Callahan Timothy P.
Englund Terry L.
Pericom Semiconductor Corp.
LandOfFree
ESD-protection device with active R-C coupling to gate of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with ESD-protection device with active R-C coupling to gate of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD-protection device with active R-C coupling to gate of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3042556