Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal
Reexamination Certificate
2001-07-12
2003-07-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Reexamination Certificate
active
06589804
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to systems and methods for regulating the formation of dielectric layers in non-volatile semiconductor memory devices.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts towards scaling down device dimensions (e.g., at sub micron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller feature sizes and separations between such features are required. This can include the thickness and spacing of dielectric materials, oxide
itride (ON) and/or oxide
itride/oxide (ONO) materials, interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit can be formed on a single wafer. Generally, the process involves creating several layers on and/or in a substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and/or on the semiconductor wafer surface. Insulation and conductivity between such electrically active regions can be important to reliable operation of such integrated circuits. One type of integrated circuit in which insulation and conductivity between electrically active regions is important is electronic memory.
Electronic memory comes in different forms to serve different purposes. One such electronic memory, FLASH memory, can be employed for information storage in devices including, but not limited to, cellular phones, digital cameras and home video game consoles. FLASH memory can be considered a solid state storage device, in that functionality is achieved electronically rather than mechanically. FLASH memory is a type of EEPROM (Electrically Erasable Programmable Read Only Memory) chip. FLASH memories are a type of non-volatile memory (NVM). NVMs can retain information when power to the NVM is removed which distinguishes NVMs from volatile memories (e.g., DRAM, SRAM) that lose data stored in them when power is removed. FLASH memory is electrically erasable and reprogrammable in-system. The combination of non-volatility and in-system eraseability/reprogrammability make FLASH memory well-suited to a number of end-product applications including, but not limited to, a personal computer BIOS, telecom switches, cellular phones, internetworking devices, instrumentation, automotive devices and consumer-oriented voice, image and data storage devices (e.g., digital cameras, digital voice recorders, PDAs).
An exemplary FLASH memory can have a grid of columns and rows with a cell that has two transistors at each intersection of the rows and columns. Thus, referring initially to Prior Art
FIG. 1
, a cross section of an exemplary FLASH memory cell
100
is illustrated. The exemplary FLASH memory cell
100
illustrated includes a control gate
102
and a floating gate
106
separated by an ON and/or ONO layer
112
. The control gate
102
can be referred to as a “poly 2” while the floating gate
106
can be referred to as a “poly 1”, and thus the term interpolydielectric can be applied to the ON and/or ONO layer
112
. Properties of the ON and/or ONO layer
112
including, but not limited to, thickness and uniformity, are important to facilitating reliable operation of the memory cell. Furthermore, properties of the ON and/or ONO layer
112
including, but not limited to, thickness and uniformity, are important to facilitating reliable interactions between the control gate
102
and the floating gate
106
. Properties of the ON and/or ONO layer
112
are thus important to facilitating reliable operation of the FLASH memory cell
100
, due to the insulating and/or conducting property of the ON and/or ONO layer
112
. For example, properties including, but not limited to the ability to store data, to retain data, to be erased, to be reprogrammed and to operate in desired electrical and temperature ranges can be affected by the thickness and/or uniformity of the ON and/or ONO layer
112
. The control gate
102
, floating gate
106
and ON and/or ONO layer
112
can be fabricated on a tunnel oxide layer
108
. It is to be appreciated that although the ON and/or ONO layer
112
is illustrated as one layer, that such a layer can be formed from multiple layers (e.g., oxide, nitride, oxide (so called ONO)). It is to be further appreciated that although the FLASH memory cell illustrated in Prior Art
FIG. 1
employs an interpolydielectric, that the present invention can be applied to the formation of charge trapping dielectrics in SONOS (Silicon Oxide Nitride Oxide Silicon) type memory devices and MONOS (Metal Oxide Nitride Oxide) devices.
The requirement of small features with close spacing between adjacent features in FLASH memory devices requires sophisticated manufacturing techniques including control of oxide
itride layer and/or oxide
itride/oxide layer formation. Fabricating a FLASH memory device using such sophisticated techniques may involve a series of steps including the formation of layers/structures by chemical vapor deposition (CVD) and oxide growth. Conventionally, difficulties in forming, with precise thickness and/or uniformity, an oxide layer over a nitride layer or a polysilicon, have limited the effectiveness and/or properties of FLASH memory devices manufactured by conventional techniques. Similarly, difficulties in forming, with precise thickness and/or uniformity, a nitride layer over an oxide layer have likewise limited the effectiveness of FLASH memory devices manufactured by conventional techniques.
Due to the extremely fine structures that are fabricated on a FLASH memory device, controlling the formation of oxide and/or nitride materials used to separate components (e.g., control gate, floating gate) on a wafer from other components are significant factors in achieving desired critical dimensions and operating properties and thus in manufacturing a reliable FLASH memory device. The more precisely the oxide and/or nitride can be formed the more precisely that critical dimensions may be achieved, with a corresponding increase in FLASH memory reliability. Conventionally, due to non-uniform oxide and/or nitride formation and inaccurate oxide and/or nitride formation monitoring techniques, a thickness of oxide and/or nitride greater or lesser than the thickness desired may be formed.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides for a system that facilitates monitoring and controlling ON and/or ONO dielectric formation. An exemplary system may employ one or more light sources arranged to project light on one or more oxide and/or nitride layers on a wafer and one or more light sensing devices (e.g., photo detector, photo diode) for detecting light reflected by the one or more oxide and/or nitride layers. The light, reflected from one or more oxide and/or nitride layers is indicative of at least the oxide and/or nitride thickness, which may vary during the oxide and/or nitride formation process.
One or more oxide
itride formers can be arranged to correspond to a particular wafer portion. Each oxide
itride former may be responsible for forming an oxide and/or nitride portion of an ON and/or ONO formation on one or more particular wafer portions. The oxide
itride former
Halliyal Arvind
Singh Bhanwar
Subramanian Ramkumar
Amin & Turocy LLP
Le Thao
Nelms David
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