Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-06-21
2003-04-22
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S543000, C323S313000
Reexamination Certificate
active
06552603
ABSTRACT:
BACKGROUND
1. Field
This patent specification relates to a voltage reference generation circuit comprising MOS or CMOS transistors, and an apparatus incorporating such generation circuit exemplified by a power source, which is suitably in use for relatively small electronic devices such as hand-held cellular phones, for example.
2. Discussion of the Background
As the use of hand-held apparatuses becomes more widespread, numerous efforts have been made to provide reliable power supplies for these apparatuses with appropriate voltage reference generation circuits.
It has been disclosed previously in Japanese Laid-Open Patent Application No. 56-108258 to provide a voltage reference generation circuit including a depletion-mode MOS transistor with its gate and drain interconnected to be utilized as a constant current source. In that disclosure, the gate and the drain of the depletion-mode MOS transistor Q
1
are interconnected as shown in
FIG. 1
, in which a constant current from the MOS transistor is supplied to succeeding transistor circuits.
Namely, each having a gate and a drain interconnected, enhancement-mode MOS transistors Q
12
and Q
13
are further connected in series to be operated by the constant current supplied by the MOS transistor Q
1
. Reference voltages are then obtained from the voltages generated by these transistors Q
12
and Q
13
.
Incidentally, the MOS transistors Q
1
, Q
12
and Q
13
are all of N-channel type. In addition, the portion of the transistors Q
12
and Q
13
illustrated in
FIG. 1
may be displaced by either a single transistor (
FIG. 6
) or more than two transistors. Also shown in
FIG. 1
are a couple of junctions and values of the potential voltages, V
0
2
and V
0
3
, at respective junctions.
In the case of the above noted single transistor illustrated in
FIG. 6
, a reference voltage is obtained as the difference between the threshold voltage V
t
—
d of depletion-mode MOS transistor Q
21
and the voltage at V
t
—
e of enhancement-mode MOS transistor Q
22
.
There is an embodiment in Application 4-65546 regarding to methods for forming MOS transistors Q
21
and Q
22
(
FIG. 6
) having different values of threshold voltage, in which the difference is affected by varying the impurity concentration in substrates and/or channel regions of respective transistors, that is achieved by, for example, changing the number of ions in ion implantation process steps.
Although no description is found in that disclosure for utilizing the above noted two transistors Q
12
and Q
13
(FIG.
1
), it is noted that threshold difference in depletion-mode MOS transistor Q
1
, and enhancement-mode MOS transistors Q
12
and Q
13
, such as described herein below, may similarly be effected by varying impurity concentrations in substrates and/or channel regions.
In addition to the voltage reference generation circuit of
FIG. 1
, a further voltage reference generation circuit may alternatively be formed as illustrated in
FIG. 2
, which includes a MOS transistor having its gate and drain interconnected so as to serve as a constant current source.
Referring to
FIG. 2
, there included in the circuit are the same depletion-mode MOS transistor Q
1
as that of
FIG. 1
, an enhancement-mode MOS transistor Q
2
having a low threshold voltage V
t
l and another enhancement-mode MOS transistor Q
3
having a higher threshold voltage V
t
h. In this construction of the voltage reference generation circuit, a reference voltage is obtained as the difference between these threshold voltages V
t
h and V
t
l of the enhancement-mode MOS transistors Q
3
and Q
2
, respectively.
FIG. 3
includes graphical plots of (I
ds
)
½
as a function of V
gs
for the MOS transistors Q
1
, Q
2
and Q
3
at a saturated drain voltage, where I
ds
is the drain current and V
gs
is the voltage between gate and source. The conductance factor K is assumed the same for respective transistors.
Since the gate and source of MOS transistor Q
1
are interconnected and the value of V
gs
is therefore zero and fixed, the constant current supplied by Q
1
is found to be I
constant
as shown in FIG.
3
. Accordingly, the values of V
gs
for satisfying the relation I
ds
=I
constant
are found to be V
0
2 and V
0
3 for the transistors Q
2
and Q
3
, respectively. The reference voltage V
REF
is subsequently obtained as the difference between these two values;
V
REF
=
V
0
3
-
V
0
2
=
V
t
h
-
V
t
l
.
The V
REF
value is therefore obtained as the difference between two thresholds V
t
h and V
t
l.
Several advantages may be noted in regard to the generation of the reference voltage V
REF
with this generation circuit, which follows.
(1) Since the V
REF
value is obtained as the difference between threshold values, as mentioned above, the dispersion V
REF
is relatively unaffected by the fluctuation of constant current, which is caused by the dispersion of the threshold voltage of the depletion-mode MOS transistor. As a result, the dispersion of V
REF
is relatively small.
(2) Because of the approximately same temperature characteristics of the MOS transistors Q
2
and Q
3
, the dependency of V
REF
value on temperature is relatively small, and (3) since the present circuit may be formed consisting of as few as three MOS transistors, the present circuit can be fabricated with more ease in a smaller area than the bandgap reference circuit.
As is known, this bandgap reference circuit is designed with a PN junction so as to output a relatively small voltage reference V
REF
having a considerably reduced temperature coefficient, utilizing both its base-emitter voltage V
be
and thermal voltage V
t
(=kT/q, where k is Boltzman's constant, T the absolute temperature and q the electron's charge). It may also be added in this context that these voltages V
be
and V
t
have the opposite polarity of temperature dependence to thereby generate compensating resultant voltages, which are appropriately utilized in this circuit.
For the aforementioned single transistor case illustrated in
FIG. 6
, the relation between threshold voltages and voltage reference from the generation circuit may be considered in a similar manner, which follows.
FIG. 7
includes graphical plots of (I
ds
)
½
as a function of V
gs
for the aforementioned MOS transistors Q
21
and Q
22
at a saturated drain voltage, where I
ds
is the drain current and V
gs
is the voltage between gate and source. The conductance factor K is assumed same for respective transistors.
Since the gate and source of MOS transistor Q
21
are interconnected and V
gs
is therefore zero and fixed, the constant current supplied by Q
21
is found to be I
constant
as shown in FIG.
7
. Accordingly, the V
gs
value of the transistor Q
22
for satisfying the relation I
ds
=I
constant
is found as to be V
REF
,
V
REF
=V
t
—
e−V
t
—
d.
As a result, the V
REF
value is given as the difference between two threshold voltages V
t
—
e and V
t
—
d.
Several advantages can also be noted in regard to the reference voltage generation with the present circuit, which follows. (1) Because of the approximately same temperature characteristics of the MOS transistors Q
21
and Q
22
, the dependency of V
REF
value on temperature is relatively small, and (2) since the present circuit may be formed consisting of as few as two MOS transistors, the present circuit can be fabricated with more ease in a smaller area than the aforementioned bandgap reference circuit.
In addition, the present circuit can offer another advantage. Namely, after a slight modification thereof, exemplified by a wire connection change of the gate of MOS transistor Q
21
, another voltage reference generation circuit can be formed, which is capable of supplying relatively small reference voltages (Japanese Laid-Open Patent Application No. 8-335122). The thus formed generation circuit is illustrated in
FIG. 8
, in which the gate of MOS transistor Q
21
is grounded, indicating the difference from the
FIG. 6
circuit after the modification.
The above noted capability of
Callahan Timothy P.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Englund Terry L.
Ricoh & Company, Ltd.
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