Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-03-19
2003-04-08
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S189050
Reexamination Certificate
active
06545940
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit. More specifically, it relates to a semiconductor integrated circuit that acquires an external signal in synchronism with an external clock signal.
Recently, a semiconductor integrated circuit, such as a synchronous DRAM (hereinafter referred to as SDRAM), has been used to operate at high speed in synchronism with an external clock signal. In a clock-synchronized type semiconductor integrated circuit, timing signals are generated to drive the associated internal circuits using the external clock signal.
For example, in the SDRAM, an address acquisition signal is generated in synchronization with an external clock signal. The SDRAM acquires an external address signal in accordance with the address acquisition signal and supplies the address signal to an internal circuit. For the purpose of high performance, the high-speed operation of the SDRAM is required. However, the high speed of the SDRAM results in a short pulse width of the address acquisition signal, if the cycle of the external clock signal is short. This makes the address acquisition of the external address signal difficult. Therefore, it is desired to have a semiconductor integrated circuit that acquires the external address signal precisely.
FIG. 1
is a schematic block diagram of a portion of a conventional SDRAM
100
. The SDRAM
100
includes an input buffer circuit
11
, a latch circuit
12
and a decoder circuit
13
.
The input buffer circuit
11
receives an external address signal ADD from an external device and amplifies the external address signal ADD.
The latch circuit
12
latches the amplified external address signal provided by the input buffer circuit
11
in accordance with an internal clock signal clkz and supplies the latch signal to the decoder circuit
13
. The internal clock signal clkz is generated by a control circuit (clock buffer) and is synchronized with an external clock signal.
The decoder circuit
13
acquires the latch signal provided by the latch circuit
12
in response to an address acquisition signal ralz. The address acquisition signal ralz is generated in response to an external command by another control circuit (command decoder). The address acquisition signal ralz is synchronized with the internal clock signal clkz.
As shown in
FIG. 2
, the input buffer circuit
11
includes a plurality (even number, for example, two) of inverter circuits
21
,
22
and provides the amplified external address signal ADD to the latch circuit
12
.
The latch circuit
12
includes first and the second latches
23
,
24
. A transfer gate
25
of the first latch
23
is turned on in response to the internal clock signal clkz having a high level and is turned off in response to the internal clock signal clkz having a low level. A transfer gate
26
of the second latch
24
is turned on in response to the internal clock signal clkz having a low level and is turned off in response to the internal clock signal clkz having a high level. The first latch
23
latches the amplified external address signal provided by the input buffer circuit
11
in response to the internal clock signal clkz having a high level. The second latch
24
latches the external address signal latched by the first latch
23
in response to the internal clock signal clkz having a low level and outputs a latch signal SGl having a level of the external address signal.
The decoder circuit
13
includes an input circuit having a latch
27
. A transfer gate
28
of the latch
27
is turned on in response to the address acquisition signal ralz having a high level and is turned off in response to the address acquisition signal ralz having a low level. The latch
27
latches the latch signal SG
1
of the latch circuit
12
during the period when the address acquisition signal ralz is at the high level and outputs a latch signal SG
2
having a level of the latch signal SG
1
.
As shown in
FIG. 3
, the SDRAM
100
generates the internal clock signal clkz using the external clock signal CLK. The latch circuit
12
outputs the latch signal SG
1
in response to a falling edge of the internal clock signal clkz. The SDRAM
100
receives a command cmd in response to a rising edge of the external clock signal CLK and generates an address acquisition signal ralz having a high level in response to a falling edge of the internal clock signal clkz for a predetermined period.
The latch
27
of the decoder circuit
13
latches the latch signal SGl in response to the address acquisition signal ralz having a high level and outputs the latch signal SG
2
having the level of the latch signal SGl from the first rising edge to the next rising edge of the address acquisition signal ralz.
Since the latch
27
drives a circuit, such as a decoder circuit that uses the latch signal SG
1
, the address acquisition signal ralz for latching the latch signal SG
1
should be maintained at high level for a predetermined period.
If the cycle of the external clock signal CLK is short in accordance with the high-speed operation, the pulse width of the address acquisition signal ralz should be short. This is because that if the pulse width of the address acquisition signal ralz is relatively long, the address acquisition signal ralz is spanned to the next cycle and the next external address signal is erroneously latched. However, if the pulse width of the address acquisition signal ralz is short in accordance with the pulse width of the external clock signal CLK, a latch period is short, so that it is difficult for the latch
27
to latch signals precisely.
In order to maintain an address acquisition signal ralz at a high level for a predetermined period, it has been proposed that a delay circuit be used. However, a delay circuit is susceptible to many external factors, such as variations in the process. Accordingly, it would be difficult to control the pulse width of the address acquisition signal ralz using a delay circuit for obtaining a desired pulse width.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit that acquires an external signal precisely in a high speed operation.
In a first aspect of the present invention, a semiconductor integrated circuit is provided. The circuit includes an internal circuit for acquiring an external signal in response to an acquisition signal. A first holding circuit is connected to the internal circuit to hold the external signal for a predetermined period in response to a holding signal and to provide the held external signal to the internal circuit. A control circuit is connected to the first holding circuit to generate the holding signal using the acquisition signal.
In a second aspect of the present invention, a semiconductor integrated circuit is provided. The circuit includes a first control circuit for generating an internal clock signal using an external clock signal and also generating an acquisition signal using the external clock signal and a control signal. An internal circuit is connected to the first control circuit to acquire an external signal in response to the acquisition signal. A first holding circuit is connected to the first control circuit to hold the external signal in response to the internal clock signal and generate a first held external signal. A second holding circuit is connected to the first holding circuit and the internal circuit to hold the first held external signal for a predetermined period in response to the holding signal and supply a second held external signal to the internal circuit. A second control circuit is connected to the first control circuit and the holding circuit to generate the holding signal using the acquisition signal.
In a third aspect of the present invention, a semiconductor integrated circuit is provided. The circuit includes a first control circuit for generating an internal clock signal using an external clock signal and also generating an acquisition signal using the external clock signal and a control signal. An internal cir
Ishida Yoshiyuki
Takashima Satoshi
Le Thong
Nelms David
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