Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-11-28
2003-01-14
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S233100
Reexamination Certificate
active
06507532
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a high speed DRAM (Dynamic Random Access Memory) used for an embedded DRAM and the like. In particular, the invention relates to a row-related control circuit of the high speed DRAM.
2. Description of the Background Art
FIG. 25
is a schematic diagram illustrating an arrangement of row-related circuitry of a conventional DRAM. DRAM shown in
FIG. 25
is a clock synchronous DRAM (SDRAM) having a 4-bank structure and storage capacity of 64 Mbits.
Referring to
FIG. 25
, the DRAM includes four memory mats MMA-MMD allocated respectively to banks A-D. Memory mats MMA-MMD each have the storage capacity of 16 Mbits. Memory mats MMA-MMD are each divided into 16 memory sub blocks MSB each having the storage capacity of 1 M bit. In each of memory mats MMA-MMD, a sense amplifier band SAB including a sense amplifier circuit for sensing, amplifying and latching data in a memory cell of a selected row is arranged between memory sub blocks MSB adjacent to each other.
Row-related control circuits CTA-CTD are respectively associated with memory mats MMA-MMD, and row-related control circuits CTA-CTD each receive externally supplied clock signal extCLK, row address signal RA<
11
:
0
>, bank address signal BA<
1
:
0
>and a command (not shown) to generate a row-related control signal. Row-related control circuits CTA-CTD generate, when designated by bank address signal BA<
1
:
0
>, row predecode signals X_A<
19
:
0
>-X_D<
19
:
0
> and block selection signals BS_A<
7
:
0
>-BS_D<
7
:
0
> according to row address signal RA<
11
:
0
> applied in synchronization with external clock signal extCLK. 8-bit block selection signal allows two memory sub blocks MSB in a bank (memory mat) designated by bank address signal BA<
1
:
0
> to be selected.
When a row-related command (bank activation command; active command) is supplied, row-related control circuits CTA-CTD are selectively activated according to bank address signal BA<
1
:
0
> so as to generate row address enable signals RADE_A-RADE_D and word line activation signals RXT_A-RXT_D in synchronization with external clock signal extCLK.
Row-related control circuits CTA-CTD are arranged corresponding to respective memory mats MMA-MMD and these row-related control circuits CTA-CTD are selectively driven according to bank address signal BA<
1
:
0
>, so that banks A-D can be driven independently into an active state.
For each memory sub block MSB of memory mats MMA-MMD, there are provided a spare determination circuit (fuse box)
4
for determining whether or not a defective row is addressed, and a row decode circuit
5
for driving memory cells of one row in an associated memory sub block into a selected state according to a corresponding block selection signal among block selection signals BS_A<
7
:
0
>-BS_D<
7
:
0
> and a corresponding predecode signal among row predecode signals X_A<
19
:
0
>-X_D<
19
:
0
>. In each of memory mats MMA-MMD, word line selection is performed in each memory sub block MSB and repair of a defective row is done by a redundant row (row spare circuit) in each memory sub block MSB. High-order signal RA<
11
:
9
>of the row address is decoded so as to generate block selection signals BS_A<
7
:
0
>-BS_D<
7
:
0
> when respective row-related control circuits CTA-CTD are activated. Row predecode signals X_A<
19
:
0
>-X_D<
19
:
0
> are generated from row address signal RA<
8
:
0
>.
FIG. 26A
illustrates a structure of a row-related control signal generation circuit of the row-related control circuit.
FIG. 26A
representatively shows one row-related control circuit CT since row-related control circuits CTA-CTD have the same structure.
Referring to
FIG. 26A
, row-related control circuit CT includes a composite gate circuit
900
receiving active command ACT instructing bank activation and precharge command PRG instructing bank inactivation, a latch circuit
901
for latching an output signal of composite gate circuit
900
in synchronization with rising of internal clock signal CLK, a delay circuit
902
for delaying, by predetermined time D
1
, bank activation signal RASE received from latch circuit
901
, an AND circuit
903
receiving an output signal of delay circuit
902
and bank activation signal RASE, a delay circuit
904
for delaying, by predetermined time D
2
, an output signal of AND circuit
903
, and an OR circuit
905
receiving an output signal of delay circuit
904
and an output signal of AND circuit
903
to generate row address enable signal RADE. Delay circuit
902
and AND circuit
903
constitute a rise delay circuit while delay circuit
904
and OR circuit
905
constitute a fall delay circuit.
Row-related control circuit CT further includes a delay circuit
906
for delaying bank activation signal RASE by predetermined time D
3
, an AND circuit
907
receiving an output signal of delay circuit
906
and bank activation signal RASE, a delay circuit
908
for delaying an output signal of AND circuit
907
by predetermined time D
4
, and an OR circuit
909
receiving an output signal of delay circuit
908
and an output signal of AND circuit
907
to generate word line activation signal RXT.
Composite gate circuit
900
is equivalent to a circuit that includes an OR circuit receiving bank activation signal RASE and active command ACT and a gate circuit receiving an output signal of the OR circuit and precharge command PRG. The gate circuit operates as a buffer circuit when precharge command PRG is in an inactive state of L (logic low) level. Internal clock signal CLK generated from external clock signal extCLK is a clock signal synchronized with external clock signal extCLK. Now, an operation of row-related control circuit CT shown in
FIG. 26A
is described in conjunction with the timing chart shown in FIG.
26
B.
In cycle #0 of clock signal CLK, active command ACT is supplied and an output signal of composite gate circuit
900
rises to H (logic high) level. The output signal of composite gate circuit
900
is latched by latch circuit
901
synchronously with rising of internal clock signal CLK, and bank activation signal RASE rises to an active state of H level. After bank activation signal RASE rises to H level, an output signal of AND circuit
903
rises to H level after delay time D
1
of delay circuit
902
has passed, and accordingly row address enable signal RADE rises to H level.
In response to rising of bank activation signal RASE, an output signal of AND circuit
907
rises to H level after delay time D
3
of delay circuit
906
has passed, and accordingly word line activation signal RXT rises to H level.
Although active command ACT falls to L level, latch circuit
901
is brought into latched state in synchronization with rising of internal clock signal CLK so that bank activation signal RASE is maintained in the active state of H level.
In clock cycle #1, when active command ACT is not supplied (when active command ACT is at L level), bank activation signal RASE is at H level and accordingly an output signal of composite gate
900
is at H level so that latch circuit
901
takes in and latches a signal of H level from composite gate
900
. In this way, bank activation signal RASE is maintained in the active state of H level until precharge command PRG is supplied (precharge command PRG attains H level), and accordingly row address enable signal RADE and word line activation signal RXT each are maintained in the active state of H level.
In clock cycles #1-#4, a column-related operation is performed (a read command instructing a data reading or a write command instructing a data writing is supplied).
In clock cycle #5, when precharge command PRG is supplied, an output signal of composite gate
900
falls to L level, latch circuit
901
takes in a signal of L level from composite gate circuit
900
at the rising edge of internal cl
Arimoto Kazutami
Fujino Takeshi
Inoue Kazunari
Yamazaki Akira
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Tran M.
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