Method of reducing micro-scratches during tungsten CMP

Details Method of reducing micro-scratches during tungsten CMP Method of reducing micro-scratches during tungsten CMP

2002-02-19

2003-04-15

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S693000, C438S785000, C438S424000, C257S770000

Reexamination Certificate

active

06548409

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to chemical-mechanical polishing (CMP) and, more particularly, to a method of reducing micro-scratches during tungsten CMP.
2. Description of the Related Art
In the fabrication of semiconductors such as very large scale integrated (VLSI) or ultra-large scale integrated (ULSI) circuits, a high degree of surface planarity is an important factor in forming high-density devices using a photolithographic operation. Especially when the fabrication of semiconductors reaches the sub-half-micron stage, chemical-mechanical polishing (CMP) method has become one of the principle means of global planarization in VLSI or ULSI production.
CMP is a preferred method of planarizing tungsten interconnects, vias and contacts. In tungsten CMP processing, a highly selective polish rate for tungsten as compared to the dielectric is allowed for over-polishing while still achieving a flat tungsten stud. However, wafer defects during polishing, such as micro-scratches, which may cause short or open circuits in the inter-metal dielectric (IMD) layer of via structure must still be overcome. The prior art teaches various methods of controlling the micro-scratches by the proper manufacturing of the abrasive particles in slurry and the proper mixing sequence of the abrasive particles with the suspension agent in slurry. Unfortunately, prior CMP slurries have not been as effective as needed.
FIGS. 1A
to
1
D are sectional views showing a conventional tungsten CMP process. First, as shown in
FIG. 1A
, a semiconductor substrate
10
has a plurality of first conductive layers
12
and an IMD layer
14
of silicon oxide formed on the first conductive layers
12
. Then, as shown in
FIG. 1B
, using anisotropic dry etching, a plurality of via structures
16
are formed in the IMD layer
14
to expose the tops of the first conductive layers
12
, respectively. Next, as shown in
FIG. 1C
, a second conducive layer
18
of tungsten (W) metal is deposited on the IMD layer
14
to fill the via structures
16
till reaching a predetermined thickness. Finally, as shown in
FIG. 1D
, in etching back the second conductive layer
18
, CMP is applied to polish the second conductive layer
18
to obtain a planar surface. Thus, the second conductive layer
18
remaining in the via structure
16
serves as a tungsten plug
19
.
In tungsten CMP processing, a slurry containing colloidal silica or dispersed aluminum mixed with basic solution, such as KOH or NH4OH solution, is employed. The interaction between the abrasive particles within the slurry and the surface of the IMD layer
14
produces small undesirable micro-scratches on the polished surface. Unfortunately, portions of a metal layer in subsequent processing become trapped within the IMD layer
14
, resulting in poor performance of the finished semiconductor device. For example, the “trapped” portion of the metal layer may produce a short circuit condition within the finished device, or undesirably high electrical leakage between adjacent metal lines. In addition, if the IMD layer
14
is also removed in the tungsten CMP process, an oxide layer erosion and a tungsten plug recess will happen due to an over-polishing.
In order to solve the micro-scratches problem, one conventional method is to develop soft slurry without abrasive particles, such as soft silica-gel like compositions. However, use of the soft slurry encounters problems of poor uniformity, decreased wafer throughput, increased process cost, and control difficulties. Another method is to tune the CMP recipe or modify the CMP steps. But, how to develop an available CMP recipe or step still challenge engineers in worldwide.
SUMMARY OF THE INVENTION
The present invention provides a method of reducing micro-scratches during tungsten CMP to solve the problems caused in the prior art.
The method of the present invention provides a novel tungsten CMP on a semiconductor substrate having at least a tungsten plug and an IMD layer. First, the tungsten CMP with a standard tungsten slurry is provided on the exposed surfaces of a tungsten plug and a IMD layer. Tungsten CMP with an oxide slurry is then provided on the polished surfaces of the tungsten plugs and the IMD layer.
Accordingly, it is a principle object of the invention to use the oxide slurry to reduce micro-scratches in the tungsten CMP.
It is another object of the invention to reduce micro-scratches in the tungsten CMP to prevent a short circuit condition within the finished device.
Yet another object of the invention is to reduce micro-scratches in the tungsten CMP to prevent undesirably high electrical leakage between adjacent metal lines.
It is a further object of the invention to reduce micro-scratches in the tungsten CMP by an easily controlled process.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.


REFERENCES:
patent: 6060370 (2000-05-01), Hsia et al.
patent: 6313039 (2001-11-01), Small et al.
patent: 10-284596 (1998-10-01), None
patent: 10-362753 (2000-07-01), None

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