Digital modulator and digital demodulator

Details Digital modulator and digital demodulator Digital modulator and digital demodulator

1999-10-15

2003-01-14

Chin, Stephen (Department: 2634)

Pulse or digital communications

Receivers

C375S261000, C375S332000, C329S306000

Reexamination Certificate

active

06507625

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital modulators and digital demodulators with quadrature amplitude modulation (QAM) schemes, and more specifically, to a digital modulator and a digital demodulator used in multiplexed channel radio communications equipment, cable television (CATV) systems, and the like.
2. Description of the Related Art
The use of digital signal processing technologies has become dominant in actual implementation of modulators and demodulators with quadrature amplitude modulation (QAM) schemes. It is because the digital technologies, when compared to analog technologies, provide better accuracy and enable easier integration of QAM functionalities into an LSI chip. However, as the number of data bits for each symbol is increased, it becomes necessary to expand the scale of digital circuits of a modulator or demodulator in order to process an increased amount of data, thus causing some problems in costs and power consumption of the circuits. To solve such problems, designers have been urged to devise some methods of reducing the scale of digital modulator and demodulator circuits. In such a circumstance, the present invention provide solutions for the increasing demands.
The following items (i) to (v) will explain some specific configurations of conventional QAM modulators and demodulators, for basic understanding of backgrounds of their potential problems.
(i)
FIG. 18
is a block diagram showing a conventional digital modulator. Two baseband signals of an in-phase channel (I-ch) and a quadrature channel (Q-ch) are supplied to their respective roll-off filters
101
and
102
for rejecting off-range frequency signals to minimize the intersymbol interference. The two roll-off filters
101
and
102
have identical internal structure as shown in FIG.
19
.
Referring to
FIG. 19
, flip-flops
103
a
,
103
b
,
103
c
, and so on are connected in series, each of which actually carries a multiple-bit value representing each instant amplitude of a baseband signal. Being triggered at intervals of T/4, those flip-flops successively provide the entered baseband signals with T/4 delays, where T is the cycle period of a carrier clock signal. The delayed baseband signals are then supplied to their respective multipliers
104
a
,
104
b
,
104
c
, and so on, which separately multiply the signals by predetermined tap coefficients &agr;
n
, &agr;
n−1
, &agr;
n−2
, and so on at T/4 intervals. An adder
105
then collects the resultant products for calculating their summation at every T/4 period. The tap coefficients are designed to yield a desired impulse response, and the different values are symmetrically arranged along that multiplier array as shown in
FIG. 19
, with a coefficient &agr;
0
placed at the central tap.
Returning to
FIG. 18
, the outputs of the roll-off filters
101
and
102
are provided to multipliers
106
and
107
for simultaneous multiplication by two orthogonal carrier signals, cos &ohgr;t and sin &ohgr;t, respectively. The multiplier
106
multiplies the output of the roll-off filter
101
by a carrier signal cos &ohgr;t at T/4 intervals, while the other multiplier
107
multiplies the output of the other roll-off filter
102
by another carrier signal sin &ohgr;t at the same intervals. An adder
108
calculates a sum of their products at T/4 intervals, thus obtaining a modulated signal in the form of a sequence of digital values. A digital-to-analog (D/A) converter
109
converts this modulated signal into an analog signal also at T/4 intervals. A low-pass filter
110
eliminates alias components, or undesired harmonic frequencies, included in the output of the D/A converter
109
.
Assume here that the frequency f of the carrier signals cos &ohgr;t and sin &ohgr;t is equal to the symbol rate. Since the multipliers
106
and
107
operate at intervals of T/4 as described before, the actual waveforms of the carrier signals, cos &ohgr;t and sin &ohgr;t, applied to them can be expressed as:
cos &ohgr;t=[1, 0, −1, 0, . . . ]  (1a)
sin &ohgr;t=[0, 1, 0, . . . ]  (1b)
Let the output signal sequence of the roll-off filter
101
be [I
1
, I
2
, I
3, I
4
, . . . ], and that of the roll-off filter
102
be [Q
1
, Q
2
, Q
3, Q
4
, . . . ]. Based on the values shown in the expressions (1a) and (1b), the modulated signal entered to the D/A converter
109
will be expressed as [I
1
, Q
2
, −I
3
, −Q
4
, . . . ].
The result of the above discussion allows such an alternate circuit configuration as illustrated in
FIG. 20
, where the multipliers
106
and
107
and adder
108
in
FIG. 18
are replaced with a combination of inverters
115
and
116
and a parallel-to-serial (P/S) converter
117
.
In a digital modulator circuit of
FIG. 20
, the I-ch baseband signal is supplied to two roll-off filters
111
and
112
and the Q-ch baseband signal is entered to two roll-off filters
113
and
114
. These four roll-off filters
111
-
114
, having the same internal structure as shown in
FIG. 19
, operate at a rate of four times as high as the carrier frequency (or the symbol rate, in this case). The P/S converter
117
has four input terminals A, B, C, and D. The inputs A and B are connected directly to the output of the roll-off filters
111
and
113
, respectively. On the other hand, the inputs C and D receive inverted signals of the outputs of the roll-off filters
112
and
114
via inverters
115
and
116
, respectively. At the rate of four times the carrier frequency, the P/S converter
117
sequentially and cyclically selects one of those inputs from A toward D and feeds the selected signal to the D/A converter
109
.
Such an alternate circuit configuration as shown in
FIG. 20
is disclosed in Japanese Patent Laid-open Publications No. 3-265332 (1991) and No. 6-104943 (1994), for example.
(ii) Carrier frequency used in a digital modulator is normally selected to be an integral multiple of its symbol rate, namely, n times the symbol rate. As clarified in
FIG. 18
, a digitally modulated signal is converted to an analog signal by the D/A converter
109
at T/4 intervals. This D/A conversion process will cause some alias frequency components imposed in the spectrum of the resultant analog signal, of which central frequencies derive from the cycle time of the D/A conversion. The alias can be filtered out by using the low-pass filter
110
. As the carrier frequency is lowered, the cutoff frequency of the low-pass filter
110
should also be reduced. Because low-pass filters with low cutoff frequencies are costly in general, a higher carrier frequency is desirable for cost reduction of modulator devices. Therefore, when the ratio of carrier frequency to symbol rate is n:1 (n is an integer), it is desired to set this factor n as high as possible.
(iii)
FIG. 21
is a block diagram showing a combination of a conventional digital modulator and demodulator. The modulator shown on the left hand of
FIG. 21
has basically the same structure as that in
FIG. 18
, while
FIG. 21
includes some more details. The following description will focus on its distinctive points, maintaining consistent reference numerals for the common elements.
In
FIG. 21
, a carrier clock signal having a frequency
(i.e., n times the symbol rate) is produced by a carrier frequency oscillator
120
. A splitter
121
then divides it into two ways and delivers one as is to the multiplier
106
, as well as supplying the other to the multiplier
107
with a phase shift of 90 degrees. Another oscillator
122
generates a signal having a frequency equal to difference between a radio frequency
and the carrier frequency
. This
signal is provided to a frequency converter
123
for upconversion of the low-pass filter output. That is, while the frequency content of a modulated signal produced by the low-pass filter
110
is centered around the carrier frequency
, the frequency converter
123
shifts it upward to higher radio frequencie

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