Flash memory having separate read and write paths

Details Flash memory having separate read and write paths Flash memory having separate read and write paths

2001-12-12

2003-09-02

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185330

Reexamination Certificate

active

06614691

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to flash memories and in particular the present invention relates to a flash memory device having separate read and write paths.
BACKGROUND OF THE INVENTION
A flash memory is a type of non-volatile memory that retains data even after power has been removed from the memory. A flash memory device has a memory array that is divided into a plurality of individual blocks of memory cells. The memory cells in each block are arranged in row and column fashion. Each block can be independently erased with respect to other blocks in the memory array.
Each flash memory cell (cell) has a source, a drain, a floating gate and a control gate. In each memory block, the control gates of each cell in a row are coupled to an associated word line. Moreover, the drains of each cell in a column are coupled to an associated bit line. In addition, the sources of each cell in the memory block are coupled to a source line. To write to or program a cell, a positive voltage is applied to a word line coupled to the control gate of the cell. In addition, a positive voltage is applied to the bit line coupled to the drain of the cell while the source line voltage is held at ground. These voltages are applied so that the programmed cell has charge stored on its floating gate.
To read a cell, a positive voltage is applied to a word line coupled to a control gate of the cell. Moreover, a relatively small positive voltage is also applied to the bit line of the drain of the cell while the source is held at ground. The current conducted by the memory cell is measured to determine a data state. A block of memory is erased by placing the control gates of each memory cell in the block to ground while applying a relatively high voltage to the source line. In addition, the drain of each memory cell is left floating (open) during an erase operation. Thus the memory cells are erased by removing charge from the floating gate.
In selecting cells to program or read from, flash memory devices implement multiplexer circuits or decoder circuits. A multiplexer circuit is a logic device that selects between two or more inputs in providing an output. The multiplexer circuits are used to selectively couple desired voltages in writing to and reading from selected cells. One multiplexer, which can be referred to as an X decoder, is coupled to the word lines to select among the rows. Another multiplexer, which can be referred to as a Y multiplexer, is coupled to the bit lines to select between the columns. Multiplexer circuits generally comprise transistors formed in integrated circuits. Typically, the transistors in a multiplexer are formed with an oxide layer of approximately 200 Å having relatively long channel lengths. With an oxide layer of approximately 200 Å, the transistor can effectively handle 4 to 12 volts. Traditionally, the Y multiplexer is used to couple approximately 5.5 volts to a selected bit line during write operations and to provide a path to a circuit comprising sense amplifiers during read operations. At a program voltage of about 5.5 volts, the transistors supply a DC current of approximately 0.5 to 1 m Amps to the selected cell to be programmed.
A synchronous flash memory is a type of flash memory. Like a typical flash memory array, a synchronous flash memory has a memory divided in a plurality of erasable array blocks. However, unlike a typical flash memory, a synchronous memory is driven by a clock. In particular, a synchronous flash memory is designed to interface with typical SDRAM systems. Moreover, unlike a typical flash memory device that typically reads 16 cells at one time, synchronous flash memories can read 4,000 or more cells at one time. Generally, this requires the memory to have a sense amplifier for each bit line. Because of the increased number of sense amplifiers used in a synchronous flash memory, the speed in which the signals are transferred from the cells to the sense amplifiers (the “read path”) is more of an issue in synchronous flash memory than in typical flash memory devices.
The transistors used in the Y multiplexer in the typical flash memory device are relatively high voltage transistors that are capable of delivering current with little voltage drop. These transistors tend to be relatively large and tend to add a relatively large amount of capacitance in the write and read paths. This capacitance reduces the speed of signals through the paths. Since, relatively low voltage transistors are all that is typically required in a read path, and relatively low voltage transistors allow for faster signals, the relatively high voltage transistors required for the write path unnecessarily slow signals in the read path.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device having a relatively fast read path.
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention, and will be understood by reading and studying the following specification.
In one embodiment, a non-volatile memory device is disclosed. The nonvolatile memory device includes a memory array, a first multiplexer and a second multiplexer. The memory array has non-volatile memory cells arranged in columns and rows. Each memory cell in a column is coupled to an associated bit line. The first multiplexer is coupled to a first end of each bit line to select bit lines during write operations to the memory array. The second multiplexer is coupled to a second end of each bit line to select bit lines during read operations from the memory array.
In another embodiment, a flash memory device comprises a memory array having erasable blocks of memory cells, a state machine, a Y multiplexer and a latch/sense amplifier circuit. Each block of memory cells is arranged in row and column fashion. Each column of memory cells is coupled to an associated bit line. The state machine is used to control memory operations to the memory array. The Y multiplexer is used to select bit lines during write operations. The Y multiplexer is coupled to the state machine to receive select commands. Moreover, the multiplexer is coupled to a first end of the bit lines. The latch/sense amplifier circuit is used to selectively read memory cells. The latch/sense amplifier circuit is coupled to the state machine to receive select commands. The latch/sense amplifier circuit is further coupled to a second end of the bit lines.
In another embodiment, a flash memory device comprises a memory array, a first multiplexer and a second multiplexer. The memory array is comprised of non-volatile memory cells arranged in columns and rows. Each memory cell in a column is coupled to an associated bit line. The first multiplexer is coupled to select bit lines during write operations to the memory array. The second multiplexer is coupled to select bit lines during read operations from the memory array.
In another embodiment, a flash memory system comprises a processor, a memory array, control circuitry, a first multiplexer, and a second multiplexer. The processor is used to provide external commands and external data. The memory array is used to store data. Moreover, the memory array has blocks of memory cells arranged in rows and columns. Each memory cell in a column has a drain coupled to an associated bit line. The control circuitry is used to control memory operations. The control circuitry is coupled to the processor to receive the external commands. The first multiplexer is coupled to select among the bit lines during write operations. The first multiplexer is coupled to each bit line. The first multiplexer is further coupled to receive select commands from the control circuitry. The second multiplexer is coupled to select among the bit lines during read operations. The second multiplexer is coupled to each bit line. The second m

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