Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2000-02-07
2003-04-08
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S758000, C257S532000, C257S536000, C257S753000
Reexamination Certificate
active
06545354
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-035759, filed Feb. 15, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having columnar electrodes on re-wiring.
There is known a semiconductor device called CSP (Chip Size Package). When the semiconductor device is to be mounted on a circuit board, a mounting technique called “face down bonding” is employed. In the case of this type of semiconductor device, columnar electrodes for connection with the circuit board, etc. are provided on a semiconductor substrate or via an intermediate substrate (interposer).
FIG. 7A
is a cross-sectional view showing an example of this type of conventional semiconductor device, and
FIG. 7B
is a cross-sectional view taken along line
7
B—
7
B in
FIG. 7A
in the state in which a protection film
5
and the elements provided thereon are removed. This semiconductor device includes a semiconductor substrate
1
which is, e.g. a silicon substrate.
The semiconductor substrate
1
has a rectangular shape, as shown in
FIG. 7B. A
central region defined by a dot-and-dash line in
FIG. 7B
serves as a circuit element formation region
2
. Where the semiconductor device is an LSI for driving a liquid crystal display panel, an oscillation circuit, a regulator circuit, an LC driver circuit, etc., although not shown, are provided in the circuit element formation region
2
. A plurality of connection pads
3
are provided on an upper surface of the semiconductor substrate
1
on the outside of the circuit element formation region
2
. Each connection pad
3
is formed of one end portion of a wiring segment
3
a
extended from the circuit element formation region
2
of semiconductor device
1
. Each connection pad
3
is connected to the LC driver circuit, etc. via the wiring segment
3
a.
An insulating film
4
formed of, e.g. a semiconductor oxide, and protection film
5
formed of, e.g. polyimide are successively provided on the upper surface of semiconductor substrate
1
excluding the central portion of each connection pad. Thus, the central portion of the connection pad
3
is exposed via an opening portion
6
defined by the protection film
5
. A re-wiring segment
7
is provided so as to extend from the exposed upper surface of the connection pad
3
to an upper surface of the protection film
5
on the circuit element formation region
2
. A distal end portion of the re-wiring segment
7
functions as an external connection pad portion
7
a
. A columnar electrode
8
is provided on an upper surface of the external connection pad portion
7
a
. A sealing film
9
made of, e.g. an epoxy resin is provided over the entire upper surface of the assembly excluding the columnar electrodes
8
. Although not shown, solder bumps are provided on the columnar electrodes
8
, and this semiconductor device is connected to a circuit board, etc. via the solder bumps.
In the above semiconductor device, the re-wiring segments
7
are provided on the protection film
5
in the circuit element formation region
2
, as mentioned above. Various signals flow through the re-wiring segments
7
since the re-wiring segments
7
function as interconnection wiring between the external circuit board, etc., on the one hand, and the circuits provided within the circuit element formation region
2
, on the other. It is thus necessary to prevent crosstalk between the re-wiring segments
7
and the oscillation circuit, etc. provided in the circuit element formation region
2
. For this purpose, it is necessary in the prior art to dispose the re-wiring segments
7
so as not to overlap in plan the oscillation circuit, etc. Because of this, the re-wiring segments
7
cannot freely be arranged, and there are very serious limitations to the design thereof.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor device, such as a CSP, having a re-wiring provided over a circuit element formation region of a semiconductor substrate, and having columnar electrodes for connection with a circuit board provided on the re-wiring, wherein the re-wiring can be freely positioned without restrictions.
In order to achieve the above object, the present invention provides a first semiconductor device including a semiconductor substrate which has a circuit element formation region at a central portion thereof and a plurality of connection pads at a peripheral portion of the circuit element formation region. A first insulating film is provided over an upper surface of the semiconductor substrate excluding the connection pads. A ground potential layer connected to the connection pads with ground potential is provided on an upper surface of the first insulating film over the circuit element formation region, and a re-wiring is provided over the ground potential layer with a second insulating film interposed. Since the ground potential layer serving as a barrier layer for preventing crosstalk is provided between the re-wiring and circuit element formation region, even if the re-wiring overlaps in plan an oscillation circuit, etc. provided within the circuit element formation region, they are electrically insulated by the ground potential layer and no crosstalk occurs therebetween. Therefore, the re-wiring can be freely arranged with no restrictions.
Alternately, in order to achieve the above object, the invention provides a second semiconductor device which, like the above-described device, the ground potential layer is provided over the circuit element formation region with the insulating film interposed, and, in addition, a thin-film circuit element such as a thin-film inductor and/or a thin-film transformer is provided over the ground potential layer with an insulating film interposed. Since the ground potential layer serving as a barrier layer for preventing crosstalk is provided between the thin-film circuit element and circuit element formation region, even if the thin-film circuit element overlaps in plan an oscillation circuit, etc. provided within the circuit element formation region, they are electrically insulated by the ground potential layer and no crosstalk occurs therebetween. Therefore, the thin-film circuit element can be freely arranged with no restrictions.
In order to achieve the above object, in the third semiconductor device, as described above, a first ground potential layer is provided over the circuit element formation region with an insulating film interposed, and a thin-film circuit element is provided over the first ground potential layer with an insulating film interposed. In addition, a second ground potential layer is provided over the thin-film circuit element with an insulating film interposed, and a re-wiring connected to the connection pads is provided over the second ground potential layer with an insulating film interposed. Since the first ground potential layer serving as a barrier layer prevents crosstalk between the thin-film circuit element and the oscillation circuit, etc. on the circuit element formation region, the thin-film circuit element can be freely arranged with no restrictions. Moreover, the second ground potential layer serving as a barrier layer prevents crosstalk between the re-wiring and the thin-film circuit element, and the re-wiring can be freely arranged with no restrictions.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 4322778 (1982-03-01), Barbour et al.
patent: 4617193 (1986-10-01), Wu
patent: 4811082 (1989-03-01), Jacobs et al.
patent: 4903116 (1990-02-01), Kohsiek
patent: 5317433 (1994-05-01), Miyawaki et
Aoki Yutaki
Mihara Ichiro
Wakabayashi Takeshi
Watanabe Katsumi
Casio Computer Co. Ltd.
Ha Nathan W.
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