Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-09-18
2003-04-22
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S292000
Reexamination Certificate
active
06552612
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to data communication receivers and, more particularly, to a stepped gain amplifier having improved attenuation.
BACKGROUND OF THE INVENTION
Low noise amplifiers (LNAs) are often used for the front-end of data communication receivers, such as satellite receivers for digital TV, which are commonly referred to as set-top boxes (STBs). The purpose of a low noise amplifier is to boost the strength of the signal received from an aerial antenna before further signal processing is attempted. Signals received from aerial antennas typically have large dynamic ranges, such as 50 dB in the STB case.
Conventional circuit configurations in these applications include a fixed gain LNA followed by a variable gain amplifier (VGA). The VGA allows the dynamic range of the signal presented to the subsequent processing blocks to be reduced, which enables operation at more optimum signal levels. The VGA is typically capable of both amplifying and attenuating the signal, as determined by its control input.
One problem with the conventional circuit configuration relates to limitations imposed by the power supply. If the received signal amplitude is very small, a high gain LNA can be used to optimize the signal-to-noise ratio. However if the received signal amplitude is large, the high gain LNA would attempt to amplify the signal amplitude above the level of the power supply voltage rails. This results in signal distortion. A compromise is therefore required, and the maximum fixed gain that can be applied in the LNA is limited by the supply voltage level.
When discrete transistors were used to implement LNAs, this limitation was not too severe. However with the desire for higher levels of circuit integration, the LNA circuitry has been moved on-chip. Therefore more stringent supply voltage limitations are applied to the maximum gains of embedded LNAs. As process technology improves, the supply voltages on integrated circuits have continued to reduce, and the limitations become more severe. For example, the core supply voltages for complementary metal oxide semiconductor (CMOS) circuits have recently been reduced from 5 Volts to voltages such as 3.3 Volts, 2.5 Volts and 1.5 Volts.
One design for working around this limitation includes the use of a switched gain LNA. A switched gain LNA avoids amplifying large input signals and reduce the dynamic range of the input signals as early as possible in the signal chain. One implementation of a switched gain LNA includes a pair of differential transconductor amplifiers which share common load networks. By using common load networks, the transconductance of each amplifier is proportionately translated into gain. In the simplest implementation, only one of the transconductance amplifiers is enabled at any one time. Gain changing is achieved by scaling the transconductances of the two amplifiers relative to one another. For input signals having a low amplitude, the amplifier having a high transconductance is enabled. For input signals having high amplitudes, the amplifier having a low transconductance is enabled. This prevents the amplifiers from attempting to amplify high input signals above the supply rail voltages.
However, the amplifier having a high transconductance significantly increases the parasitic capacitances that are coupled to the output load of the LNA. These excess parasitic capacitances can cause reduced amplifier bandwidth and can cause frequency response anomalies. Improved switched gain amplifiers are therefore desired.
SUMMARY OF THE INVENTION
One embodiment of the present invention is directed to a switched gain differential amplifier which includes first and second differential transconductance amplifier stages and a disabled dummy differential transconductance amplifier stage. The first and second differential transconductance amplifier stages have respective differential in puts that are coupled in-phase to one another and respective differential outputs that are coupled in-phase to one another. At least one of the stages is selectively enabled. The disabled dummy differential transconductance amplifier stage has a differential input coupled in-phase to the differential inputs of the first and second differential transconductance amplifier stages and a differential output cross-coupled out-of-phase to the differential outputs of the first and second differential transconductance amplifier stages. A common load circuit is coupled to the differential outputs of the first and second differential transconductance amplifier stages and the disabled dummy differential transconductance amplifier stage.
Another embodiment of the present invention is directed to a switched gain differential amplifier having first and second differential transconductance amplifier stages and a dummy differential transconductance amplifier stage. The first and second differential transconductance amplifier stages have respective differential inputs that are coupled in-phase to one another and respective differential outputs that are coupled in-phase to one another. At least one of the first and second stages is selectively enabled and has a parasitic capacitance coupled between the differential input and the differential output of that stage. The dummy differential transconductance amplifier stage is coupled between the differential inputs of the first and second differential transconductance amplifier stages and the differential outputs of the first and second differential transconductance amplifier stages for canceling the parasitic capacitance.
Another embodiment of the present invention is directed to a method of canceling parasitic capacitance in a switched gain differential amplifier. The method includes receiving a differential input signal and amplifying the differential input signal with at least one of first and second differential transconductance amplifier stages. The first and second differential transconductance amplifier stages have differential inputs that are coupled in-phase to one another and differential outputs that are coupled in-phase to one another. At least one of the first or second stages is selectively enabled and has a parasitic capacitance coupled between the differential input and the differential output of that stage. An effect of the parasitic capacitance is canceled with a disabled dummy differential transconductance amplifier stage having a differential input coupled in-phase to the differential inputs of the first and second differential transconductance amplifier stages and a differential output cross-coupled out-of-phase to the differential outputs of the first and second differential transconductance amplifier stages.
REFERENCES:
patent: 5903185 (1999-05-01), Cargill
patent: 5926068 (1999-07-01), Harr
LSI Logic Corporation
Nguyen Khanh Van
Pascal Robert
Westman Champlin & Kelly
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