Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
1997-01-30
2003-04-29
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S337000, C327S362000, C330S009000
Reexamination Certificate
active
06556072
ABSTRACT:
TECHNICAL FIELD
This invention relates to switched capacitor circuits, in particular to a switched capacitor filter with reduced harmonic distortion.
BACKGROUND OF THE INVENTION
A switched capacitor circuit, also referred to briefly as SC circuit in literature, is a circuit capable of processing sampled analog signals using clock signals and switching circuit means driven by such signals.
An example of an SC circuit is the SC integrator shown in
FIG. 1
, which constitutes a basic circuit block for obtaining an SC filter.
In this case, the four switching means of the circuit, denoted by SW
1
, SW
2
, SW
3
and SW
4
in the drawing figure, are electronic switches implemented with MOS transistors, and are driven each by two discrete non-overlapping phase clock signals.
In principle, there should occur no alterations to the charge stored in the capacitors of the SC circuits, and accordingly, the charge transfers should be exact ones.
However, due to the presence of parasitic capacitances associated with the channels of the MOS transistors used as switching means, this is not what precisely happens in actual practice.
In fact, these parasitic capacitances store an amount of charge which is proportional to the signal that appears at the terminals of the respective switching means, and when these charges are injected into the capacitors, the event produces a voltage offset in the system if said signal is a constant (DC) one, or an error in gain and an amount of harmonic distortion in the output signal if said signal is a varying one.
Several methods are described in literature for reducing this cause of harmonic distortion in switched capacitor circuits, although it is stated by D. G. Haigh and B. Singh in an ISCAS 1983 paper “A switching scheme for switched capacitor filters which reduces the effect of parasitic capacitances associated with switch control terminals” that in SC circuits with two non-overlapping phase clock signals, said harmonic distortion can never be brought below a definite level, calculated at around 40-50 dB.
This is indeed due to the presence of said parasitic capacitances associated with the channel of the MOS transistors employed as the switching means.
The solution proposed in the report mentioned above for reducing said harmonic distortion to a minimum, consists of using four discrete clock signals with non-overlapping phases, a method known to the skilled ones in the art as “four-phase clocking”.
In another paper, “On switch-induced distortion in switched capacitor circuits”, ISCAS 1988, D. G. Haigh and J. T. Taylor state that in switched capacitor filters, harmonic distortion never drops below values in the −68 dB range, not even when a four clocking signals system is used.
To solve the problem, it is proposed therein of increasing the transition time for the phases of the clocking signals to change from one state to the other.
However, if SC filters are to be designed with even lower harmonic distortion levels, the last-mentioned approach is no longer proposable because it would involve a very long transition time.
In the circuit shown in
FIG. 1
, which is an SC integrator of conventional construction, the electronic switches shown at SW
1
, SW
2
, SW
3
and SW
4
in the drawing figure may each comprise, for example, a pair of n-channel MOS transistors, or pair of p-channel transistors, or pair of CMOS transistors.
The latter choice is the most comprehensive one, and an obligatory one for values of the input/output signals comparable with the power supply ones.
The two transistors jointly making up a switch are driven by two clocking signals which do not overlap in time, such as the signals F
1
and F
2
and the signals F
1
a
and F
2
a
, whose waveforms are shown in FIG.
2
.
For an analysis of the effect of the charges stored in the channel by the MOS transistors, one should consider the input circuit of the integrator, shown best in
FIG. 3
, which comprises a capacitor C
3
and the two switches SW
3
and SW
4
.
Similar considerations would apply to the other switched capacitor C
2
being feedback connected, together with the switches SW
1
and SW
2
, to the operational amplifier included in the integrator.
The two n-channel MOS transistors, M
1
and M
2
, which make up the switch SW
3
, are driven by the clocking signals F
1
and F
2
, respectively, with the two transistors M
3
and M
4
of the switch SW
4
being driven by the signals F
1
a
and F
2
a
, respectively.
As shown in
FIG. 2
, the signal F
1
a
changes in level before the signal F
1
, and the signal F
2
a
changes in level before the signal F
2
.
The charges stored in the channels of the transistors M
1
and M
2
, in the conduction state, of the switch SW
3
are not injected into the capacitor C
3
because, upon such transistors being cut off by the drive signals F
1
and F
2
, the other end of the capacitor C
3
is floating, in that the signals F
1
a
and F
2
a
are at a low already.
The charges which are stored into the transistors M
3
and M
4
of the switch SW
4
will now be considered.
Upon M
3
being cut off, the charge stored in its channel is partly injected into the capacitor C
3
.
This amount of charge is, however, constant at all times, because the voltage across M
3
is fixed (virtual ground of an operational amplifier) and the other end of the capacitor C
3
is also connected to a fixed (ground) voltage reference via the transistor M
2
, which transistor is still in a conduction state.
This constant charge injection produces a voltage offset in the output signal, but no harmonic distortion.
The charge stored up in the transistor M
4
, which, in the transition to the cutoff state from the conduction state is injected into the capacitor C
3
, is a non-constant quantity, despite the voltage across M
4
being a fixed (ground) one, because the other end of the capacitor C
3
, connected to a circuit node denoted by B in
FIG. 3
, is at the input voltage VIN.
The circuit node B sees, toward ground, an intrinsic parasitic capacitance Cp which is due to the source and drain diffusions of the two transistors M
1
and M
2
, and a conduction resistance RON of the transistor M
1
.
As those familiar with the art will readily recognize, both the capacitance Cp and the resistance RON have a non-linear pattern versus voltage.
Since the voltage at the circuit node B varies with the voltage of the input signal VIN, it follows that the impedance seen toward ground from the circuit node B, and consisting of a parallel of the parasitic capacitance Cp and the conduction resistance RON of the transistor M
1
, will also vary with the input voltage.
This causes the amount of the charge injected into the capacitor C
3
by the transistor M
4
to be non-constant and vary with the input signal Vin, thereby adversely affecting the system linearity and introducing harmonic distortion in the output signal.
Therefore, it can be appreciated that there is a great need for SC circuits having a lower harmonic distortion than prior art SC circuits, without significantly increasing the circuit complexity and the area required for integration as an integrated circuit.
The advantages of an SC circuit according to the invention will be apparent from the description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention is embodied in a switched capacitor circuit with low distortion having a circuit input terminal. The circuit includes a first switching element with the first switch terminal coupled to the circuit input terminal and a second switch terminal coupled to a reference level. The first switching element also includes a switch common terminal and a switch control to alternatively couple the switch common terminal to either the first or second switch terminals at a predetermined switching rate. The first switching element has a non-linear parasitic capacitance from the switch common terminal to the reference level and a non-linear conduction resistance from the first switch terminal to the swit
Nagari Angelo
Nicollini Germano
Iannucci Robert
Jorgenson Lisa K.
Le Dinh T.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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