Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2003-01-23
2003-09-02
Tokar, Michael (Department: 2819)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S014000, C331S016000, C331S011000, C331S00100A, C331S010000
Reexamination Certificate
active
06614319
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a phase-locked loop circuit and, more particularly, to a phase-locked loop circuit of fractional frequency-dividing type.
BACKGROUND OF THE INVENTION
In order to control the frequency of an output signal at a frequency interval smaller than the frequency of a reference signal, the conventional practice is to employ an arrangement which averages, in terms of time, a frequency dividing ratio of a programmable frequency dividing circuit with the frequency dividing ratio being variable in an ordinary phase-locked loop (PLL) to implement a frequency dividing ratio of an accuracy finer than a decimal-point by using the average value. A configuration in which the dividing ratio of a frequency dividing circuit is changed and averaged in terms of time to implement fractional frequency division in equivalent terms is also referred to as a fractional frequency-dividing system.
If one period 1/fr of a reference signal of which frequency is fr is adopted as one clock, then, by switching the frequency dividing ratio from M to M+1 only once over L clocks (time T), the average value of the dividing ratio over the time T will be given by M+1/L.
By extending the term 1/L of this fractional part to k/L, where k=0, 1, 2, . . . , the frequency dividing ratio can be set at steps of 1/L. The frequency-dividing ratio is given as follows.
Mave=
M+k/L
(0
=<k=<L
, where
k
is an integer)
FIG. 15
is a block diagram illustrating the structure and principle of such a fractional frequency-dividing PLL circuit. A phase comparator, a charge pump, a loop filter and a voltage-controlled oscillator of the PLL circuit have been deleted from the diagram of
FIG. 15
; only a frequency dividing circuit and a control circuit thereof are shown. As illustrated in
FIG. 15
, the PLL circuit is constituted by an accumulator
600
comprising an adder
602
and a register
603
, and a variable frequency dividing circuit
601
for dividing frequency at a dividing ratio M or M+1 (where M is a predetermined integer). The adder
602
performs addition at increments of k in response to a clock whose frequency is equal to a reference frequency. The frequency dividing ratio of the frequency divider becomes M+1 when the adder
602
overflows and is M when the adder
602
does not overflow.
When the dividing ratio is changed periodically, as in the fractional frequency dividing scheme of the arrangement shown in
FIG. 15
, a spurious having frequency components of a period of this change is generated. In other words, if T represents a period of the change in the frequency dividing ratio of the frequency dividing circuit
601
, then in the output of the PLL circuit (the output of the voltage-controlled oscillator) is generated spurious frequency components which are equally spaced by a frequency interval 1/T from the center frequency of the output of the voltage-controlled oscillator.
In order to reduce this spurious component, the specification of Japanese Patent Application Laid-Open No. 8-8741 discloses an arrangement of the kind shown in
FIG. 16
as a frequency synthesizer (PLL circuit) for controlling output-signal frequency at frequency intervals that are smaller than a reference-signal frequency, thereby reducing spurious components in the vicinity of the center frequency of the output signal. The arrangement shown in
FIG. 16
includes a phase comparator
701
, a low-pass filter
702
, a voltage-controlled oscillator
703
, a variable frequency divider
704
, a frequency dividing adder
711
, accumulators
706
to
709
, and a frequency-division control circuit
705
. In accordance with a value set from the frequency-division control circuit
705
, the variable frequency divider
704
divides and outputs the frequency of the output signal from voltage-controlled oscillator (VCO)
703
. The phase comparator
701
compares a phase of the output of the variable frequency divider
704
and a phase of a reference frequency and outputs a phase difference. The output of the phase comparator
701
is input to the voltage-controlled oscillator
703
via the low-pass filter
702
and control is performed in such a manner that the signal obtained by frequency-dividing the Output signal of the voltage-controlled oscillator
703
will be synchronized to the reference signal. The Output of the voltage-controlled oscillator
703
is delivered as the output signal and is input to the variable frequency divider
704
.
The frequency-division control circuit
705
comprises accumulators
706
,
707
,
708
, and
709
, a fractional part calculating circuit
710
and the frequency dividing ratio adder
711
Each of these circuits operates with the output of the variable frequency divider
704
serving as the clock. The accumulator
706
, which comprises an adder and a register, adds the value of the register to a fractional data, which has been provided externally, synchronizing with the clock, and updates the register. The accumulator
707
, which comprises an adder and a register, adds the output value of the accumulator
706
to the value of its register in sync with the clock, thereby adding 1 to the least significant bit, and updates the values value of its register. The accumulators
707
and
708
are identically constructed. The adder of each accumulator outputs the carry signal of its most significant bit and inputs the carry signal to the decimal calculating circuit
710
.
The fractional part calculating circuit
710
operates in synchronization with the clock. When the accumulator
706
generates a carry signal, the fractional part calculating circuit
710
generates +1 after three clock pulses. When a carry signal enters from the accumulator
707
, the fractional part calculating circuit
710
generates +1 after two clock pulses and +1 after three clock pulses. When a carry signal enters from the accumulator
708
, the fractional part calculating circuit
710
generates in turn +1 after one clock pulse; −2 after two clocks pulses a +1 after three clock pulses. When a carry signal enters from the accumulator
709
, the fractional part calculating circuit
710
generates in turn +1 after 0 clock pulses, −3 after one clock pulse, +3 after two clock pulses and −1 after three clock pulses.
The total sum of the values generated by the carry signals produced by each of the accumulators at each clock is output to the fractional part calculating circuit
710
. The frequency dividing adder
711
adds the decimal output of the fractional part calculating circuit
710
and the value of the integer, and the result becomes the output of the frequency-division control circuit
705
, which sets the dividing ratio of the variable frequency divider
704
. As a result, a change in the dividing ratio is produced clock by clock, the frequency components of the change in dividing ratio are raised and the low frequency components are lowered. The changes in the dividing ratio brought about by the carry signals from the accumulators
707
to
709
have no influence upon the averaged dividing ratio because the respective averages over time are zero; only the carry produced by the accumulator
706
contributes to the averaged dividing ratio.
If M represents an integer data, K a fraction data and n the number of bits constituting the accumulator
706
, the accumulator
706
will generate K carries over 2
n
clocks and the dividing ratio will be made M+1 K times. The averaged dividing ratio, therefore, will be M+K/2
n
. If fr represents the frequency of the reference signal, then the output frequency will be fr·(M+K/2
n
).
Though the frequency component of a change in dividing ratio appears as a spurious Output from the VCO, the frequency of the change in dividing ratio resulting from connecting the accumulators in four stages increases and the low frequency component decreases. The periodic change is disturbed by always adding 1 to the least significant bit of the accumulator
707
a
Saeki Takanori
Tanaka Toshiyuki
Hayes & Soloway P.C.
Mai Lam T.
Tokar Michael
LandOfFree
Phase-locked loop circuit of fractional frequency-dividing type does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Phase-locked loop circuit of fractional frequency-dividing type, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop circuit of fractional frequency-dividing type will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3033615