Pulse or digital communications – Transceivers
Reexamination Certificate
1999-09-30
2003-09-23
Pham, Chi (Department: 2631)
Pulse or digital communications
Transceivers
C375S295000, C345S087000, C345S100000
Reexamination Certificate
active
06625207
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data transmission circuit and method in which data is transmitted and a liquid crystal display apparatus in which display data is transmitted and the transmitted data is displayed on a liquid crystal panel.
As the conventional data transmission circuit is known, for example, a data transmission circuit provided with an input/output interface called GTL (Gunning Transceiver Logic) or CTT (Center Tapped Termination), as disclosed by Nikkei Electronics, No. 556, Jun. 8, 1992, pp. 133 to 144 published by Nikkei BP-Sha.
In the conventional liquid crystal display apparatus, an inputted video signal is converted by a liquid crystal controller into a display data signal for input to a liquid crystal data driver. This display data signal is supplied to the liquid crystal data driver by use of a data transmission circuit as mentioned above. The liquid crystal data driver generates a liquid crystal driving voltage from the supplied display data signal and outputs the generated liquid crystal driving voltage to a liquid crystal panel, thereby effecting the display of an image. For example, in a liquid crystal display apparatus providing display with RGB×64 gradation levels (64 gradation levels for each of R, G and B) and 260 thousands of colors, display data generated by a liquid crystal controller is connected to a plurality of liquid crystal data drivers by a (RGB×6=18)-bit data bus so that the display data is transferred to each liquid crystal data driver to effect display, as disclosed by the article 23.2 in SID (SOCIETY FOR INFORMATION DISPLAY) INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS VOLUME XXV, 1994.
SUMMARY OF THE INVENTION
However, an apparatus such as a liquid crystal display apparatus using the conventional data transmission circuit has the problem of large power consumption. More particularly, as an output circuit of the data transfer circuit is used, for example, a CMOS circuit as an output circuit which transmits data represented by the voltage amplitude value of a power supply voltage, or an open drain circuit or push-pull circuit as a transmission bus in which a line is terminated. In the case where the CMOS circuit is used, a driving current flows when a bit value of output data (for example, display data) is changed. Thereby, an electric power is consumed. Thus, a possible method considered in order to reduce the power consumption is to cause the change in bit value of output data to be not made as much as possible. In the CMOS circuit, there is a fear that an operation following input data becomes insufficient as the speed of input data is higher.
On the other hand, in the open drain circuit or push-pull circuit as a transmission bus in which a line is terminated, a sufficient operation is enabled even for high-speed input data but a steady current flows irrespective of an input signal. Namely, in the case where the open drain circuit is used, a driving current does not flow unless output data has a high level. However, if the output data has a low level, a driving current flows. Thus, a possible method considered in order to reduce the power consumption is to cause the output data to be provided with a high level. Also, in the case where the push-pull circuit is used, a driving current flows with power consumption irrespective of whether the level of output data is high or low. Thus, a possible method considered in order to reduce the power consumption is to cause the output of a termination voltage level.
In recent years, the image resolving power of a liquid crystal panel has been improved with the larger size of the liquid crystal panel. Therewith, the amount of display data to be transmitted to the liquid crystal panel within a unit time is increased. Accordingly, there is the problem that the power consumption of the transmission circuit is increased more and more.
Accordingly, an object of the present invention is to provide a data transmission circuit and method in which a reduction in power consumption is enabled and a liquid crystal display apparatus which uses such data transmission circuit or method.
To attain the above object, a data transmission circuit according to one aspect of the present invention has a transmitter section sequentially inputted with n-bit parallel data (n: an integer) and a receiver section connected to the transmitter section through a transmission line, in which the n-bit parallel data is transmitted from the transmitter section to the receiver section through the transmission line. The transmitter section is provided with a first holding circuit for storing, the n-bit parallel data inputted to the transmitter section, by plural sets the number of which is not more than 2
m
(m: an integer satisfying m<n), judgement means for judging whether or not the present n-bit parallel data inputted to the transmitter section is identical to any one of the plural sets of n-bit parallel data stored in the first holding circuit, thereby outputting a first result of judgement in the case where the identification to any one of the plural sets is determined and a second result of judgement in the case where the identification to none of the plural sets is determined, hold position information output means for outputting information with m or less bits indicative of a hold position of the one set of n-bit parallel data in a second holding circuit in the case where the first result of judgement is outputted by the judgement means, and first output means for transmitting the hold position information to the receiver section through the transmission line in the case where the first result of judgement is outputted by the judgement means while transmitting, the present n-bit parallel data inputted to the transmitter section, to the receiver section through the transmission line in the case where the second result of judgement is outputted by the judgement means. In the case where the second result of judgement is outputted by the judgement means, the first holding circuit is inputted and stored with the present n-bit parallel data inputted to the transmitter section. The receiver section is provided with the second holding circuit for storing the same plural sets of n-bit parallel data as the first holding circuit, and second output means for reading, in the case where the hold position information is received through the transmission line, the one set of n-bit parallel data from the second holding circuit in accordance with the hold position information and outputting the read data from the receiver section while storing, in the case where the present n-bit parallel data is received through the transmission line, the received present n-bit parallel data into the second holding circuit and outputting the data from the receiver section.
Thus, in the present invention, in the case where the present n-bit parallel data inputted to the transmitter section is identical to any one of the plural sets of n-bit parallel data stored in the first holding circuit, information with m or less bits indicative of a hold position of the one set of n-bit parallel data in the second holding circuit is transmitted. Therefore, it is possible to make a reduction in power consumption as compared with the case where one set of n-bit parallel data is transmitted.
In an example of the present invention, each of the first and second output circuits is a circuit (for example, a CMOS circuit) for transmitting the n-bit parallel data in which data is represented by the voltage amplitude value of a power supply voltage and the first output circuit has a data holding circuit (for example, a latch circuit. In the case where the second result of judgement is outputted by the judgement means, (n−m)-bit parallel data in the present n-bit parallel data inputted to the transmitter section is transmitted from the first output circuit to the receiver section through the transmission line while the present (n−m)-bit parallel data is stored into the data holding circuit. In the case where
Higa Atsuhiro
Koshi Hirobumi
Nitta Hiroyuki
Tsunekawa Satoru
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Pham Chi
Williams Demetria
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