Preemptive timer multiplexed shared memory access

Details Preemptive timer multiplexed shared memory access Preemptive timer multiplexed shared memory access

1998-03-05

2003-05-20

Olms, Douglas (Department: 2661)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S438000

Reexamination Certificate

active

06567426

ABSTRACT:

FIELD OF THE INVENTION
The present claimed invention relates to the field of processor memory systems. More particularly, the present claimed invention relates to a processor architecture with a single memory unit that is shared among multiple processors.
BACKGROUND ART
Today's computer systems generally rely on auxiliary processors with dedicated memory units to perform various specialized tasks. In media processing in particular, the latest consumer entertainment applications utilize media processors to process video, audio, and graphics data for playing games, video and sound recordings, educational software, and the like. For example, in addition to its general media processor, a computer may include specialized processors such as a graphics processor for processing graphics data, an MPEG video decoder for decoding MPEG video data, an MPEG audio decoder for decoding MPEG audio data. Each of these specialized processors (i.e., units) typically have its own dedicated logic and memory resources. Hence, each processor adds a data memory and supporting logic circuitry to the computer.
Prior Art
FIG. 1
illustrates an exemplary computer system
100
comprised of processors with dedicated memory units. The computer system includes three separate memory units; a main memory
102
, a dedicated graphics memory
104
, and a dedicated co-processor memory
105
. The main memory
102
provides fast access to data for the signal processor
106
through a main memory controller
110
. The dedicated graphics memory
104
provides fast access to graphics data for a graphics processor
112
via a graphics memory controller
114
. Also, the dedicated co-processor memory
105
provides fast access to data used by a co-processor
116
via a co-processor memory controller
118
. In this system configuration, the signal processor has read/write access to the main memory
102
but not to the dedicated graphics memory
104
or dedicated co-processor memory
105
. Similarly, the co-processor has read/write access to the dedicated co-processor memory
105
, but not to the main memory
102
or dedicated graphics memory
104
. Likewise, the graphics processor
112
has read/write access to the dedicated graphics memory
104
but not to the main memory
102
or dedicated co-processor memory
105
.
Unfortunately, these dedicated memories and controllers for each processing unit lead to duplication of resources due to variations in compute loads of the processors and inefficient use of valuable die area in integrated chips. For example, in one moment, a user may be watching a movie on the computer. The video processing involved in playing a movie usually entails only video and audio processing. The graphics processor remains idle during this time. Conversely, the user may be playing a game on the computer. Playing a game typically requires no video processing. Only the graphics processor and audio processor may be involved in processing the data for playing the game. This means that whenever a processor is idle or inactive, its dedicated memory is not being utilized. Since the unused memory typically occupies a die area in a chip, it translates directly into costs because it is burdening the chip during the idle times.
Furthermore, some computer applications require that a processor operate on data stored in the main memory or in one of the other dedicated memory units. Whenever data stored in one particular memory unit is to be processed by a designated processor other than the processor which has access to that particular memory unit, the data must be transferred to a memory unit for which the designated processor has access. For example, certain image processing applications require that data, stored in main memory or dedicated graphics memory, be processed by the image processor. In order to enable image processor to access data stored in; main memory or in dedicated graphics memory, the data must be transferred or copied to dedicated image processor memory.
Thus, what is needed is a low cost processor architecture with a single memory unit that can be shared among a number of processors while ensuring real time performance for each processor.
SUMMARY OF THE INVENTION
The present invention is directed to a method and system for sharing a data memory among a plurality of processors in a computer system. In the system and method of the present invention, a plurality of processors are coupled to a data memory for accessing the data memory in N-bit bandwidth. The present invention receives an active signal for accessing the data memory from the plurality of processors. A processor requesting accessing to the data memory asserts an active signal. Among the processors asserting active signals, a processor is selected as a memory master to the data memory. The present invention then transfers the N-bit wide data between the selected processor and the data memory in a time slot defined by a clock cycle. Only one processor is allowed access to the data memory during a given time slot. In the preferred embodiment of the present invention, the N-bit bandwidth is large enough to accommodate the data requirements of all the processors.


REFERENCES:
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5682484 (1997-10-01), Lambrecht
patent: 5745732 (1998-04-01), Cherukuri et al.
patent: 5822767 (1998-10-01), MacWilliams et al.
patent: 6073251 (2000-06-01), Jewett et al.

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