Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-11-02
2003-01-21
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060, C365S233500
Reexamination Certificate
active
06510097
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interface circuit that controls access to a dynamic random-access memory.
2. Description of the Related Art
Dynamic random-access memory (DRAM) is used in many types of computing devices and is accessed by many types of processors. A DRAM interface circuit generates signals that control the reading and writing of data in a DRAM. The DRAM interface circuit may be integrated into a microprocessor.
Before a memory cell in a DRAM can be accessed, the row in which the memory cell is located must be activated. One of the functions of a DRAM interface circuit is to decide whether a row to be accessed is active, and if it is not, to activate it before beginning read or write access to the row. Another function is to deactivate a row when access shifts to a new row.
One type of DRAM developed for high-speed access is synchronous DRAM (SDRAM), which operates in synchronization with a clock signal and permits burst access to a plurality of memory cells in different columns in a row. Japanese Unexamined Patent Publication No. 9-106669 describes a DRAM interface circuit that extends this burst access capability to memory cells in different banks of an SDRAM.
When a conventional DRAM interface circuit performs access to a consecutive series of addresses spanning two banks, however, it exhausts the rows in the first bank before proceeding to access the second bank. Row transitions thus occur mainly within the same bank. The DRAM interface circuit in Japanese Unexamined Patent Publication No. 9-106669 permits continuous access to continue when a row transition from one bank to another occurs, but when access changes from a first row to a second row in the same bank, before issuing any Read or Write commands for the second row, the DRAM interface circuit must issue a Precharge command to deactivate the first row, wait for the precharge operation to be completed, then issue an Active command to activate the second row and wait for the second row to become active. Access is therefore interrupted for a considerable time while the first row is being deactivated and the second row is being activated. As a result, the total access time is lengthened.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a DRAM interface circuit that enables continuous access to a continuous series of addresses, regardless of whether or not the series crosses a row boundary.
The invented DRAM interface circuit controls access to a DRAM according to received address signals. The DRAM has a plurality of banks, each bank having memory cells disposed in a plurality of rows. The DRAM interface circuit includes an address decoder and an active/precharge command generator. The address decoder decodes the address signals so that if a series of address signals is received in a consecutive address sequence, whenever the series includes a transition from a first row to a second row, the first row and the second row are disposed in different banks in the dynamic random-access memory. For example, the address decoder may place the row address bits in more significant bit positions than the bank address bits, the reverse of the conventional practice. The active/precharge command generator activates the second row while the first row is being accessed, and precharges the first row while the second row is being accessed.
During consecutive address access, all row-to-row transitions occur between different banks, so access can proceed continuously from one row to the next, the new row already having been activated before the row transition occurs, and the old row being precharged during access to the new row. In particular, burst access can proceed continuously from one row to the next.
The above-mentioned second row may be activated when access to the first row begins, but the second row is more preferably activated when access reaches a designated column in the first row, most preferably a column near the end of the first row, so that power is not consumed needlessly by activating the second row earlier than necessary.
The invented DRAM interface circuit may also be used to control access to a plurality of DRAMs. The consecutive address sequence extends across the plurality of DRAMs. If the first and second rows mentioned above are disposed in a first DRAM, and a third row, directly following the second row in the address sequence, is disposed in a second DRAM, then access to the second row is briefly interrupted in order to select the second DRAM and issue an activation command for the third row. Access to the second row resumes as soon as the activation command has been issued. At the end of access to the second row, the second row is precharged, then the second DRAM is selected and the third row, which is already active, is accessed. Access to consecutive addresses can thus proceed substantially continuously from one DRAM to the next.
The DRAM or DRAMs controlled by the invented interface circuit may be, for example, synchronous DRAM cores integrated together with the invented interface circuit and a central processing unit in a single semiconductor chip, such as a microprocessor chip.
REFERENCES:
patent: 5689470 (1997-11-01), Inoue
patent: 5745913 (1998-04-01), Pattin et al.
patent: 8-129881 (1996-05-01), None
patent: 9-106669 (1997-04-01), None
Lebentritt Michael S.
Nguyen Hien
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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