Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-08-03
2003-07-15
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000
Reexamination Certificate
active
06593243
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of manufacturing semiconductor devices and, more particularly to a method of manufacturing a semiconductor device capable of forming a pattern such as an extremely fine interconnection with accuracy.
2. Description of the Background Art
Interconnections are increasingly becoming smaller in semiconductor devices. Thus, it is becoming difficult to form such extremely fine interconnection patterns only by means of lithography. To meet the requirements for such semiconductor devices, a hard mask including for example a silicon oxide film is applied in place of a photoresist pattern as a mask material.
Now, an exemplary method of manufacturing a semiconductor device using the hard mask will be described with reference to the drawings. Referring to
FIG. 13
, a polycrystalline silicon film
102
is formed for example by CVD (Chemical Vapor Deposition) on a silicon substrate
101
. A tungsten silicide film
103
is formed for example by sputtering on polycrystalline silicon film
102
. An insulating film
104
, which is to be a hard mask, is formed on tungsten silicide film
103
. A prescribed photoresist pattern
105
is formed on insulating film
104
.
Referring to
FIG. 14
, by anisotropically etching insulating film
104
using photoresist pattern
105
as a mask, a surface of tungsten silicide film
103
is exposed and insulating film
104
a
is formed.
Referring now to
FIG. 15
, by removing photoresist pattern
105
and isotropically etching insulating film
104
a
, an insulating film mask (hard mask)
104
b
is formed having a prescribed dimension.
At the time, for example, if insulating film
104
a
is a silicon oxide film, a prescribed insulating film mask
104
b
is formed by isotropically etching insulating film
104
a
in a hydrofluoric solution.
Then, by anisotropically etching tungsten silicide film
103
and polycrystalline silicon film
102
using insulating film mask
104
b
as a mask, an interconnection (not shown) having a prescribed dimension is formed. Thus, a semiconductor device is formed having fine interconnections.
As described above, insulating film mask
104
b
is formed by isotropically etching insulating film
104
a
. In a semiconductor device or the like in which insulating film mask
104
b
(hard mask) is ultimately removed after forming a desired interconnection, an extremely thin hard mask may be formed. In this case, to achieve a desired interconnection dimension, control of a thickness of insulating film
104
as the hard mask becomes extremely difficult.
As a result, when an interconnection dimension must be changed to comply with the change of a design rule of a semiconductor device, a thickness of an insulating film as a hard mask must be considered. Accordingly, it becomes extremely difficult to form a desired hard mask.
In addition, when insulating film
104
a
is isotropically etched in a hydrofluoric solution, insulating films
104
a
and
104
b
as hard masks may come off silicon substrate
101
. Thus, a desired interconnection cannot be formed.
SUMMARY OF THE INVENTION
The present invention is made to solve the aforementioned problems. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of providing a mask material with a desired dimension without any variation in thickness of the mask material and preventing a layer to be the mask material from coming off a semiconductor substrate.
The method of manufacturing the semiconductor device according to the present invention is provided with the following steps. A prescribed layer is formed on a main surface of a semiconductor substrate. A layer, which is to be used as a mask material when patterning the prescribed layer, is formed thereon. A photoresist pattern is formed on the layer to be the mask material. Using the photoresist pattern as the mask, the layer to be the mask material is etched to form the mask material. The prescribed layer is etched using the mask material as a mask to form a prescribed pattern. In the step of forming the mask material, the layer to be the mask material is etched in a gas phase ambient using the photoresist pattern as the mask.
According to the manufacturing method, in the step of forming the mask material, the layer to be the mask material is etched in the gas phase ambient using the photoresist pattern as the mask. As compared with the case of etching in a liquid phase, the mask material can be formed without causing the layer to be the mask material to come off the semiconductor substrate. In addition, as the layer to be the mask material is covered by the photoresist pattern, a desired mask material can be formed without causing any variation in thickness of the mask material. As a result, by etching the prescribed layer using the mask material as the mask, a prescribed fine pattern can readily be formed with extremely high dimensional accuracy.
More specifically, the step of forming the mask material preferably includes: a first etching step of anisotropically etching the layer to be the mask material to expose a surface of the prescribed layer using the photoresist pattern as the mask; and a second etching step of etching a side surface of the layer to be the mask material positioned under the photoresist pattern in the gas phase ambient to form the mask material.
In this case, the mask material having a desired dimension can be formed with accuracy without causing any decrease in thickness of the layer to be the mask material. Even when the dimension of a prescribed pattern is to be changed to comply with the change in design rule of a semiconductor device, for example, the thickness of the layer to be the mask material needs not be considered.
More preferably, the second etching step includes,a step of removing a polymer film formed on the side surface of the layer to be the mask material in the first etching step.
Removal of the polymer film enables uniform etching in the second etching step to form the mask material with high dimensional accuracy.
More preferably, the step of forming the photoresist pattern includes a step of forming an anti-reflection film as an underlying film, and the second etching step includes a step of etching the exposed side surface of the layer to be the mask material using the anti-reflection film as the mask.
In this case, halation is prevented by the anti-reflection film during exposure, so that a finer photoresist pattern is formed and a fine mask material can readily be formed with high dimensional accuracy.
When a silicon nitride film is applied as the layer to be the mask material, in the second etching step, etching of the layer to be the mask material preferably involves making of a gas including CF
4
, O
2
and N
2
into a plasma for etching in the plasma ambient.
Further, a thickness of the layer to be the mask material is smaller than a length over which the layer to be the mask material is etched along the main surface of the semiconductor substrate in the step of forming the mask material. The step of forming the mask material preferably includes the step of forming the mask material by isotropically etching in the gas phase ambient.
In this case, only one isotropic etching enables formation of the mask material.
When the layer to be the mask material includes a silicon oxide film, the gas phase ambient preferably includes hydrofluoric acid (HF) in a gas phase.
Preferably, the prescribed layer is a conductive layer and the prescribed pattern includes an interconnection.
In this case, an interconnection, which is the most highly required to be fine in the semiconductor device, can readily be formed with dimensional accuracy.
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patent: 5429070 (1995-07-01), Campbell et al.
patent: 5472564 (1995-12-01), Nakamura et al.
patent: 5541127 (1996-07-01), Hoshiko et al.
patent: 5856227 (1999-01-01), Yu et al.
patent: 5930594 (1999-07-01), Villain
patent: 6004853 (1999-12-01), Yang et al.
patent: 6235638 (2001-05-01), Huang et al.
patent: 6261934 (2001-07-01),
Utech Benjamin L.
Vinh Lan
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