Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-06-28
2003-09-16
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S763010, C324S537000
Reexamination Certificate
active
06621289
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit (IC) fabrication processes, and in particular to methods and test circuits for locating defects during IC fabrication process development.
BACKGROUND OF THE INVENTION
Integrated Circuit (IC) devices typically include numerous electrical and/or electronic elements that are fabricated on, for example, silicon wafers to perform a particular function. The sequence of steps that occur in the course of manufacturing an IC device can be grouped into two phases: 1) the design phase, and 2) the fabrication phase.
design phase begins by deciding upon the desired functions and necessary operating specifications of the IC device. The IC device is then designed from the “top down”; that is, large functional blocks are first identified, then sub-blocks are selected, and then the logic gates needed to implement the sub-blocks are chosen. Each logic gate is designed through the appropriate connection of, for example, transistors and resistors. The logic gates and other circuit components are then combined to form schematic diagrams. After the various levels of design are completed, each level is checked to insure that correct functionality is achieved, and then test vectors are generated from the schematic diagrams. Next, the circuit is laid out. A layout consists of sets of patterns that will be transferred to the silicon wafer. These patterns correspond to, for example, the formation of transistors and interconnect structures. The layout is designed from the “bottom up”; for example, basic components (e.g., transistors) are first laid out, then logic gates are created by interconnecting appropriate basic components, forming the logic gates into sub-blocks, and finally connecting appropriate sub-blocks to form functional blocks. Power busses, clock-lines, and input-output pads required by the circuit design are also incorporated during the layout process. The completed layout is then subjected to a set of design rule checks and propagation delay simulations to verify that a correct implementation of the circuit design has been achieved. After this checking procedure, the layout is used to generate a set of masks that are used during the fabrication phase to specify the circuit patterns on the silicon wafer.
Specifically, the fabrication phase includes a sequence of process steps during which the set of masks are used to transfer the layout patterns onto a silicon wafer using photolithographic and film formation processes. The process parameters (e.g., temperature, pressure, deposition rates and times, etch rates and times) associated with the process steps are typically developed and refined during an initial development stage. These refined process parameters are then used to produce a final fabrication process that is used during IC production runs.
Test structures formed on the wafer during the development stage of the fabrication phase are utilized to identify the precise structural nature of defects caused by nonoptimal process parameters, thereby facilitating the refinement of the final fabrication process. These test structures are necessary as the physical nature of these defects cannot be discerned from output data of the ICs. Specifically, defects in the ICs produce functional errors in the output data. These functional errors provide little or no information to identify the physical structure causing the defect. As explained in detail below, even with test structures, information about the exact location and nature of the defect is still not readily obtainable. Thus, failure analysis remains difficult and time consuming.
FIG.
1
(A) is a plan view showing a conventional semiconductor test wafer
100
including ICs
110
and conventional test structures
120
and
130
. Conventional test structures
120
and
130
are often located on test wafer
100
in a “fives”arrangement (four peripheral locations and one central location, as shown in FIG.
1
(A)). Alternatively, test structures
120
and
130
may be located in a “nines” arrangement (not shown), in which test structures
120
and
130
form a cross pattern on the wafer. Conventional test structures
120
and
130
are used to detect defects associated with the various conductive materials that are fabricated during the various process steps.
FIG.
1
(B) is a plan view showing a first conventional test structure
120
, referred to as a “fork”, that is used to detect short circuit defects. Test structure
120
includes a first terminal
121
, a second terminal
122
, a first fork structure
125
that is connected to first terminal
121
and a second fork structure
126
that is connected to second terminal
122
. The “tines” of first fork structure
125
extend between the “tines” of second fork structure
126
such that these “tines” are separated by distances associated with the design specifications of the IC
110
(see FIG.
1
(A)). One test structure
120
is formed, for example, during each diffusion formation step, metal formation step and polysilicon formation step associated with the fabrication of the IC. Short circuit defects are detected by applying a voltage source to first terminal
121
and checking for a resulting current at second terminal
122
. A current detected at second terminal
122
indicates a short circuit, thereby indicating a potential problem associated with the process step in which the shorted test structure was formed. By locating, magnifying and observing the short circuit defect, failure analysis specialists are able to refine the process step to eliminate defects in subsequent fabrication runs.
FIG.
1
(C) is a plan view showing a second conventional test structure
130
, referred to as a “serpentine”, that is used to detect open circuit defects. Test structure
130
includes a first terminal
131
, a second terminal
132
and an elongated conductive path
135
that is connected between first terminal
131
and second terminal
132
. One test structure
130
is formed, for example, during each diffusion formation step, metal formation step and polysilicon formation step associated with the fabrication of the IC. Open circuit defects are detected by applying a voltage source to first terminal
131
and checking for a resulting current at second terminal
132
. An open circuit defect is detected when a current is not detected at second terminal
132
, thereby indicating a potential problem associated with the process step in which the opened test structure was formed. By locating, magnifying and observing the nature of the open circuit defect, failure analysis specialists are able to refine the process step to eliminate defects in subsequent fabrication runs.
A first problem associated with the conventional test structures is that, even if a defect is detected, the precise location of the defect is not readily identifiable. For example, referring to FIG.
1
(B), test structure
120
indicates the same short circuit defect whether the actual defect is located at location
128
or location
129
. Similarly, referring to FIG.
1
(C), test structure
130
indicates the same open circuit defect whether the actual defect is located at location
138
or location
139
. Because the location of the actual defect is not readily identifiable, a failure analysis specialist must spend significant amounts of time locating the defect in order to analyze the cause of the defect.
A second problem associated with conventional test structures
120
and
130
is that they cover areas that are typically too small to detect defects at a parts-per-million (PPM) level. That is, because one defect anywhere in the test structure generates a defect detection event, the formation of large test structures is essentially pointless because it would be too difficult to determine whether one, two or twenty defects exist in the structure.
A third problem associated with the conventional test structures
120
and
130
is that each test structure typically indicates problems associated with only one process step or a small number of process steps. Therefore, seve
Cuneo Kamand
Hollington Jermele
Meles Pablo
Xilinx , Inc.
Young Edel M.
LandOfFree
Method and test circuit for developing integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and test circuit for developing integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and test circuit for developing integrated circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3030188