Register controlled DLL reducing current consumption

Details Register controlled DLL reducing current consumption Register controlled DLL reducing current consumption

2002-06-27

2003-07-15

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S153000

Reexamination Certificate

active

06593786

ABSTRACT:

The present application claims the priority benefit of Korean Patent Application No. 2001-38871 filed Jun. 30, 2001, under 35 U.S.C. §119, and the contents of the Korean Patent Application are herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay locked loop (DLL) in a semiconductor memory device and, more particularly, to a resister controlled DLL capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode.
2. Discussion of the Related Art
Generally, in system circuits of semiconductor devices, a clock signal has been used as a reference clock signal for adjusting operation timing or guaranteeing a high-speed operation without an error. When a clock signal from an external circuit is used in an internal circuit, a time delay (or clock skew) is generated. A DLL has been used to compensate for such a time delay by providing the same phase between the external and internal clock signals. As compared with the phase locked loop (PLL), the DLL has an advantage in that it is less sensitive to a noise than the PLL. Accordingly, the DLL has been widely used in synchronous memories such as DDR SDRAMs (Double Data Rate Synchronous DRAMs). A register controlled DLL has been generally used as a DLL circuit.
Referring to
FIG. 1
, a conventional register controlled DLL includes first and second clock buffers
11
and
12
, a clock divider
13
, a phase comparator
19
, a delay unit
10
which has first to third delay lines
14
to
16
, a delay monitor
23
having a shift register
17
and a shift controller
18
in a DLL loop, first and second DLL drivers
20
and
21
, and a delay model
22
.
The first clock buffer
11
receives an inverted external clock signal /clk and produces a first clock signal fall_clk which is synchronized with a falling edge of the clock signal clk (or a rising edge of the clock signal /clk). Likewise, the second clock buffer
12
receives the external clock signal clk and produces a second clock signal rise_clk which is synchronized with a rising edge of the clock signal clk. The clock divider
13
divides the second clock signal rise_clk into N (N: a positive integer, typically N=8) signals and then produces a reference clock signal ref and a divided clock signals div_in.
The first delay line
14
in the delay unit
10
receives and delays the first clock signal fall_clk according to an amount of delay from the shift register
17
, which is controlled by the shift controller
18
, and produces a first internal clock signal ifclk. Also, the second delay line
15
receives the second clock signal rise_clk according to an amount of delay from the shift register
17
, which is also controlled by the shift controller
18
,) and produces a second internal clock signal irclk. The first and second DLL drivers
20
and
21
receive the first and second internal clock signals ifclk and irclk and produce first and second DLL clock signals fclk_dll and rclk_dll, respectively. The third delay line
16
receives the divided clock signal div_in from the clock divider
13
and produces a delayed clock signal feedback_dly. The delay model
22
receiving the delayed clock signal feedback_dly provides the same signal processing path to the delayed clock signal feedback_dly as the actual signal processing.
The phase comparator
19
compares phases of the output signal (feed_back) from the delay model
22
with the reference clock signal ref and provides a control signal ctrl to the shift controller
18
according to the phase difference. The shift controller
18
outputs a right or left shift signal SR or SL to the shift register
17
in response to the control signal ctrl, and the first to third delay lines
14
to
16
shift the input clock signals (e.g., fall_clk and rise_clk) based on the amount of shifting stored in the shift register
17
. Also, the shift controller
18
outputs a DLL locking signal dll_lockb when there is no phase difference between the output signal from the delay model
22
and the reference clock signal ref. The delay model
22
includes a dummy clock buffer, a dummy output buffer and a dummy load, which is called a replica circuit. The shift register
17
and the shift controller
18
form the delay monitor
23
used to control the first to third delay lines
14
to
16
within the delay unit
10
.
The conventional register controlled DLL of
FIG. 1
produces two divided clocks in order to compensate for a phase difference between the first and second clock signals fall_clk and rise_clk through the clock divider
13
. That is, the clock divider
13
receives the second clock signal rise_clk and produces the reference clock signal ref and the divided clock signal div_in, each of which has a pulse width of tCK, whenever an N-th division clock signal is generated. The reference clock signal ref and the divided clock signal div_in are out of phase and the reference clock signal ref has a rising edge after tCK from a rising edge of the divided clock signal div_in. The phase of the reference clock signal ref generated after the time of tCK is compared with the delayed clock signal feedback_dly, which is produced by the delay unit
10
and the delay model
22
. The control signal ctrl, which is produced by the result of the phase comparison, is input into the shift controller
18
to control the amount of the delay.
Referring to
FIG. 2
, the divided clock signal div_in is initially delayed by a unit delay time (for convenience sake, unit delay time tD is 0.1 ns) in a unit delay element and then this is outputted as a delayed clock signal feedback_dly. The delayed clock signal feedback_dly is further delayed by a delay time (for convenience sake, this delay time tB is 3 ns) in the delay model
22
and then outputted as a delayed feedback signal feed_back. Since the initial delayed feedback signal feed_back passes through the unit delay element and the delay model
22
, the initial delayed feedback signal feed_back has a rising edge rising 3.1 ns after the rising of the edge of the divided clock signal div_in.
On the other hand, since there is a time difference between the reference clock signal ref and the divided clock signal div_in, if tCK is 15 ns, then the rising edge of the reference clock signal ref lags behind the delayed feedback signal feed_back by 11.9 ns (tCK−(tD+tB)=15 ns−3.1 ns=11.9 ns) in their phases. That is, such a phase difference, which is caused by the delay line, has to be compensated by 12 ns
(
tCK−tB=
15
ns−
3
ns=tA
(12 ns))
in order that the divided clock signal div_in has the same phase as the reference clock signal ref. In this case, 120 (12 ns/0.1 ns) unit delay lines are needed to compensate for the phase difference of 12 ns using a unit delay time of 0.1 ns thereof. Accordingly, the first clock signal fall_clk and the second clock signal rise_clk must pass through the number of required 120 unit delay lines in order to produce appropriate first and second DLL clock signals fclk_dll and rclk_dll, respectively.
As stated above, the conventional register controlled DLL requires a large number of unit delay lines to compensate for the phase difference between the reference clock signal ref and the divided clock signal div_in. As a result, a significant amount of time is required to make the phase locking and a large amount of current is consumed with the increase of chip size of the unit delay lines.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a register controlled delay locked loop (DLL) capable of decreasing the number of required delay lines, and to provide a semiconductor memory device having the DLL.
It is another object of the present invention to provide a register controlled delay locked loop (DLL) capable of reducing current consumption by using a small number of unit delay lines, and to provide a semiconductor memory device having the DLL.
In accordance with an aspect of

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