Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
1999-08-26
2003-07-01
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000, C341S155000
Reexamination Certificate
active
06587060
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of data converters, and particularly to multi-bit, high performance analog-to-digital and digital-to-analog conversion.
BACKGROUND OF THE INVENTION
Delta-sigma modular architectures for analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) based on continuous-time and switched capacitor integration are well known in the art. These architectures typically are for one bit or more modulators, one bit being the most common since the quantizers and DACs in the modulators are inherently more linear for one bit. The one bit minimizes the major sources of distortion generation in the modulator and therefore allows for high levels of spurious free dynamic range. However, a high-performance modulator of order two or more integrator stages is only conditionally stable and must incorporate substantial performance loss to maintain stability. This is especially true for the one bit modulator, since the two state output cannot instantaneously track the continuous, band limited (filtered) input signal. It is only over the band limited longer term that the output tracks the input precisely. If, on the other hand, multi-bit modulators are used, the output quantization noise level is lower to begin with, and the instantaneous output is able to more closely track with the input. This closer tracking equates to less performance loss that must be incorporated into multi-stage modulators to maintain stability. In fact, most two stage multi-bit modulators do not have to purposely add loss in order to achieve stability since sufficient loss in the actual circuit is already present. Therefore, multi-bit modulators would be the best approach for high-performance ADCs and DACs were it not for the difficulty in maintaining linearity so as to maintain the desired high level of spurious free dynamic range. Since multi-bit modulators are much more efficient in suppressing in-band noise, the oversampling ratio (sampling rate divided by twice the resolution bandwidth) can be lower, which generally equates to lower power required and/or less costly parts. It would therefore be highly desirable to provide a high-performance, multi-bit ADC or DAC modulator that provides good linearity and high spurious free dynamic range.
SUMMARY OF THE INVENTION
The present invention provides a means for acquiring and maintaining linearity in high-performance ADCs and DACs. Thus, the present invention is directed to an analog-to-digital converter. In one embodiment, the delta-sigma analog-to-digital converter modulator includes a means for modulating an analog input signal, a means for quantizing an output received from the modulating means to a three state digital code, a means for mapping an output of the quantizing means from a three state digital code to a two state digital code, a means for delaying and reordering the two state digital code output by a predetermined or random means, a means for inverse mapping the reordered two state digital code to a three state digital code, and a means for converting the resultant three state digital code to an analog signal which is connected back to the modulating means. The analog-to-digital converter thus formed is capable of converting an analog input signal to a two state digital output code with a predetermined number of bits of resolution.
The present invention is further directed to a digital-to-analog converter. In one embodiment, the delta-sigma digital-to-analog converter modulator includes a means for modulating a digital input signal being represented by a predetermined number of bits, a means for mapping an output of the modulating means from a two state signal to a three state digital code, one means per bit of the three state digital code output for converting each bit to an analog signal, and a combiner and reconstruction filter means for combining the analog signals. The digital-to-analog converter thus formed is capable of converting a digital input signal to an analog output signal at the output of the reconstruction filter means.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 5245343 (1993-09-01), Greenwood et al.
patent: 6061008 (2000-05-01), Abbey
patent: 6124813 (2000-09-01), Robertson et al
patent: 6188345 (2001-02-01), McDonald et al.
patent: 6229466 (2001-05-01), Gattani
patent: 6326912 (2001-12-01), Fujimori
patent: 6373418 (2002-04-01), Abbey
Jean-Pierre Peguy
JeanGlaude Jean Bruner
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