Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-11-29
2003-03-04
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189090
Reexamination Certificate
active
06529411
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a reference voltage generator circuit for a nonvolatile memory, and more particularly to a reference voltage generator circuit for a nonvolatile memory, which, in generating each voltage for write, erase, and verification, can provide temperature characteristics depending upon each operation mode (write/erase, verification/read) by a single band gap circuit.
BACKGROUND OF THE INVENTION
In nonvolatile semiconductor memories, after erasure or writing, write verification or erase verification is carried out to examine whether or not information has been correctly erased or written, followed by reading operation. To this end, erase verify voltage (or write verify voltage) and read voltage used as gate voltage of the memory cell at the time of erase verification (or write verification) and reading are generated by a reference voltage generator circuit within the nonvolatile semiconductor memory. Voltage is selectively sent to each word line by performing switching among the erase verify voltage, the write verify voltage, and the read voltage.
FIG. 1
shows a specific example of a conventional reference voltage generator circuit for a nonvolatile memory.
A reference voltage generator circuit
500
comprises a band gap (BGR) circuit
510
for generating an output voltage REF and a write regulator circuit
520
connected to the band gap circuit
510
. A voltage REF output from the band gap circuit
510
is input into the write regulator circuit
520
, and the write regulator circuit
520
generates an output voltage OUT based on this REF. The band gap circuit
510
comprises P-type transistors
1
,
4
,
6
, N-type transistors
2
,
5
, resistors
3
,
7
, and a diode
8
.
Each source of the P-type transistors
1
,
4
,
6
is connected to a power line. The gate and the drain of the P-type transistor
1
are commonly bonded, and this portion is connected to the drain of the N-type transistor
2
. The gate of the P-type transistor
4
is connected to the drain of the P-type transistor
1
, and the drain of the P-type transistor
4
is connected to the drain of the N-type transistor
5
. The P-type transistor
6
in its gate is connected to the drain of the P-type transistor
1
. A constant current inversely proportional to the resistance value of the resistor
3
is output from the drain of the P-type transistor
6
. The P-type transistors
1
,
4
,
6
are connected to the drain of the N-type transistor
2
in such a state that the gates of these transistors are connected parallel to one another. The source of the N-type transistor
2
is grounded through the resistor
3
, and the gate of the N-type transistor
2
is connected to the gate of the N-type transistor
5
. The source of the N-type transistor
5
is grounded, and the drain and the gate of the N-type transistor
5
each are connected to the source of the P-type transistor
6
. A circuit composed of the resistor
7
and the diode
8
, which are connected in series, is inserted between the drain of the P-type transistor
6
and the ground. An output voltage REF is output as an output of the band gap circuit
510
form the high potential side of the resistor
7
.
In the band gap circuit
510
, a constant current supplied to the series circuit composed of the resistor
7
and the diode
8
is inversely proportional to the resistance value of the resistor
3
. For this reason, a voltage drop corresponding to the resistance value of the resistor
3
, that is, a voltage drop VR set by the ratio of the resistance value R
7
of the resistor
7
to the resistance value R
3
of the resistor
3
(=reference value R
7
/resistance value R
3
), occurs in the resistor
7
. The sum of the voltage drop VR and the forward voltage VF of the diode
8
(=VR+VF) is output as an output voltage REF.
The temperature dependency &dgr;(REF)/&dgr;T of the output voltage REF is expressed by equation (1):
&dgr;(
REF
3
)/&dgr;
T
=(
k/q
)×
ln
[{(
W
4
/
L
4
)×(
W
2
/
L
2
)}/{(
W
1
/
L
1
)×(
W
5
/
L
5
)}]×{(
W
6
/
L
6
)/(
W
1
/
L
1
)}×(
R
7
/
R
3
)+(&dgr;(
VF
)/&dgr;
T
) (1)
wherein
k represents Boltzmann constant and is 1.38×e
−23
[J/K];
q represents the quantity of electric charges of electron in a simple form (elementary electric charge) and is 1.6×e
−19
[C];
T represents absolute temperature;
W
1
, W
2
, W
4
, W
5
, and W
6
respectively represent the channel widths of the transistors
1
,
2
,
4
,
5
, and
6
;
L
1
, L
2
, L
4
, L
5
, and L
6
respectively represent the channel lengths of the transistors
1
,
2
,
4
,
5
, and
6
; and
k/q is a constant;
R
3
represents the resistance value of the resistor
3
;
R
7
represents the resistance value of the resistor
7
; and
VF represents the forward voltage of the diode
8
.
This equation (1) shows that the temperature dependency &dgr;(VF)/&dgr;T of the forward voltage VF of the diode
8
usually has a negative value, and the temperature dependency &dgr;(REF)/&dgr;T of the output voltage REF can be set by the ratio of the resistance value R
7
of the resistor
7
to the resistance value R
3
of the resistor
3
, i.e., R
7
/R
3
. That is, what is required for imparting temperature dependency to the REF level is only to set the resistance value ratio R
7
/R
3
.
The write regulator circuit
520
comprises a differential amplifier
9
, a P-type transistor
10
, and a resistor
11
. The output voltage REF of the band gap circuit
510
is input into a (−) input terminal of the differential amplifier
9
, and a voltage Sref of a split terminal (split by a resistor R
10
and a resistor R
11
) of the resistor
11
is input into a (+) input terminal. The gate of the P-type transistor
10
is connected to the output terminal of the differential amplifier
9
, and the resistor
11
is connected between the drain and the ground. The source of the P-type transistor
10
is connected to a power line. The differential amplifier
9
compares the REF value input into the (−) input terminal with the Sref value input into the (+) input terminal.
In the write mode, the OUT level of the write regulator
520
is determined by equation (2) based on the ratio of split by the resistance values R
10
, R
11
of the resistor
11
:
OUT
={(
R
10
+
R
11
)/
R
10
}×
REF
(2)
Since, as described above, the REF level output from the band gap circuit
510
has been set so as not to have temperature dependence, the OUT level of the write regulator
520
is also set so as not to have temperature dependence.
In the verify mode, after writing (including writing after erase), write verification is carried out to judge whether or not information was correctly written. The memory cell of the nonvolatile memory is a kind of MOS (metal oxide semiconductor transistor) and thus is generally characterized in that the threshold voltage is high at low temperatures and decreases with raising the temperature. Therefore, in the verification after writing, setting in such a manner that the verify level is high at low temperatures and decreases with raising the temperature can realize advantageous verification because this setting conforms to the temperature characteristics of the threshold value of the memory cell. For this reason, a circuit is desired wherein the verify level decreases with raising the temperature.
The verify level having such temperature characteristics can be provided by adopting a reference voltage generator circuit having a construction shown in
FIG. 2B
described later wherein a reference voltage is generated in a band gap circuit having temperature dependence to provide a level necessary for the verify regulator circuit.
FIG. 2A
is a schematic diagram showing the construction of a conventional reference voltage generator circuit for writing which is provided with a band gap circuit and a write regulator circuit, and
FIG. 2B
a schematic diagram showing the construct
Tamura Gou
Tonda Yasuhiro
Katten Muchin Zavis & Rosenman
NEC Corporation
Tran M.
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