Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-03-19
2003-07-01
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S200000, C365S201000, C365S205000, C365S207000, C365S208000
Reexamination Certificate
active
06587377
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a nonvolatile semiconductor memory device which compares data with a level of a reference cell before outputting the data.
2. Description of the Related Art
When data is to be read from a nonvolatile semiconductor memory device, an electric current running through a memory cell transistor is compared with an electric current running through a reference cell transistor, and a HIGH/LOW status of the data is determined based on the comparison. In this configuration, the Vg-Id characteristic (i.e., gate voltage versus drain current characteristic) of a memory cell transistor is preferably the same shape as the Vg-Id characteristic of the reference cell transistor with only a horizontal shift of position.
FIG. 1
is a diagram showing Vg-Id characteristics of cell transistors under an ideal situation.
In
FIG. 1
, a Vg-Id characteristic curve
10
is that of a reference cell transistor. A Vg-Id characteristic curve
11
is that of a memory cell transistor that is in the erased state, and, thus, stores therein data “1”. A Vg-Id characteristic curve
12
is that of a memory cell transistor that is in the programmed state, and, thus, stores therein data “0”.
When a read voltage WL is applied to the gate of the memory cell transistor, and a voltage WL_ref is applied to the gate of the reference cell transistor, each cell has an electric current passing therethrough that is commensurate with the gate voltage applied thereto. In
FIG. 1
, the gate voltages WL and WL_ref are identical and represented by a vertical dotted line. An electric current passes through each transistor in an amount corresponding to the position of the intersection where the characteristic curve meets the dotted line.
In
FIG. 1
, the Vg-Id characteristic curve of each cell transistor has the same curve shape. In this case, the amounts of electric currents corresponding to the gate voltages WL and WL_ref differ from each other by a sufficient margin, so that reliable data read operation is achieved. Namely, a sufficient margin can be secured even if there are power supply voltage fluctuation and various noises.
In reality, however, the memory cell transistor and the reference cell transistor are not formed within the same array, but are formed at different locations inside a semiconductor chip. Because of this, they may have Vg-Id characteristic curves whose shapes are different from each other.
FIG. 2
is a diagram showing Vg-Id characteristics of cell transistors under a situation that is not ideal.
In
FIG. 2
, the Vg-Id characteristic curve
11
is that of a memory cell transistor that stores therein data “1”, and the Vg-Id characteristic curve
12
is that of a memory cell transistor that stored therein data “0”. A Vg-Id characteristic curve
10
a
and a Vg-Id characteristic curve
10
b
are that of a reference cell transistor. The Vg-Id characteristic curve
10
a
corresponds to a case in which the slope of the curve is greater than that of the characteristic curve of the memory cell transistor. The Vg-Id characteristic curve
10
b
corresponds to a case in which the slope of the curve is smaller than that of the characteristic curve of the memory cell transistor.
When the read voltage WL is applied to the gate of the memory cell transistor, and the voltage WL_ref is applied to the gate of the reference cell transistor, each cell has an electric current passing therethrough that corresponds to the position of the intersection where the characteristic curve meets the dotted line.
In
FIG. 2
, the reference cell has the Vg-Id characteristic curve that is a different shape from the Vg-Id characteristic curve of the memory cell. In this case, the amounts of electric currents corresponding to the gate voltages WL and WL_ref may not have a sufficient difference between the memory cell and the reference cell. Accordingly, it is difficult to secure sufficient margin in the presence of power supply voltage fluctuation and various noises.
Accordingly, there is a need for a semiconductor memory device which can adjust the slope of the Vg-Id characteristic curve of the reference cell so as to make it conform to the Vg-Id characteristic curve of the memory cell.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a nonvolatile semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
It is another and more specific object of the present invention to provide a semiconductor memory device which can adjust the slope of the Vg-Id characteristic curve of the reference cell so as to make it conform to the Vg-Id characteristic curve of the memory cell.
In order to achieve the above objects according to the present invention, a nonvolatile semiconductor memory device includes a reference circuit which includes a plurality of reference cell transistors connected together and receiving a common gate voltage, and includes a signal line having an electric current running therethrough that is a composite of electric currents running through the reference cell transistors in accordance with the gate voltage, a memory cell array which includes memory cells for storing data therein, a comparison circuit which compares the electric current running through the signal line with an electric current corresponding to data of one of the memory cells, and a threshold value setting circuit which adjusts threshold voltage levels of one or more of the reference cell transistors so as to bring a voltage versus current characteristic curve of the gate voltage and the electric current running through the signal line closer to a voltage versus current characteristic curve of the memory cells.
In the semiconductor memory device as described above, a composite of the electric currents running through the reference cell transistors is used as an electric current that is compared with memory cell data. Adjustment of threshold voltage levels of the reference cell transistors makes it possible to freely set the slope of the voltage versus current characteristic curve.
In one embodiment of the present invention, the reference cell transistors of the reference circuit include a first reference cell transistor, a second reference cell transistor connected in series to the first reference cell transistor, and a third reference cell transistor connected in parallel to the series connection of the first reference cell transistor and the second reference cell transistor, wherein the electric current running through the signal line is a sum of an electric current running through the series connection and an electric current running through the third reference cell transistor.
In another embodiment, the reference cell transistors of the reference circuit include a first reference cell transistor, a second reference cell transistor connected in series to the first reference cell transistor, and a third reference cell transistor connected in parallel to the first reference cell transistor, wherein the electric current running through the signal line is an electric current running through the second reference cell transistor.
In the configurations described above, threshold voltage levels Vt
0
, Vt
1
, and Vt
2
of the first, second, and third respective reference cell transistors are set such that Vt
1
<Vt
0
<Vt
2
. Then, one of the threshold voltage levels Vt
1
and Vt
2
is adjusted while maintaining Vt
1
<Vt
0
<Vt
2
, thereby adjusting a slope of a voltage versus current characteristic defined by the gate voltage and the electric current running through the signal line.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5091888 (1992-02-01), Akaogi
patent: 5444656 (1995-08-01), Bauer et al.
patent: 6215697 (2001-04-01), Lu et al.
patent: 63
Arent Fox Kintner & Plotkin & Kahn, PLLC
Nelms David
Yoha Connie C.
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