Nonvolatile semiconductor memory device with initialization...

Details Nonvolatile semiconductor memory device with initialization... Nonvolatile semiconductor memory device with initialization...

2000-11-08

2003-03-18

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185200, C365S185170

Reexamination Certificate

active

06535427

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-322548, filed Nov. 12, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a read circuit which read data stored in a memory cell, nonvolatile semiconductor memory device having an improved read method, and a control method thereof.
Nonvolatile memory (EEPROM) is widely known as semiconductor memory which retains data written in a memory cell with no power voltage supplied. A type of nonvolatile memory, called flash memory, can electrically erase data in a plurality of memory cells collectively.
FIG. 1
shows a schematic configuration of conventional flash memory. Each cell contains a bit line BL and a word line WL.
FIG. 1
shows just two BLs BL
0
and BL
1
and two WLs WL
0
and WL
1
. Each intersection is provided with memory cell MC comprising nonvolatile transistor, namely an FETMOS-structured transistor having a floating gate. Bit lines BL
0
and BL
1
and word lines WL
0
and WL
1
in a plurality of cells and a plurality of memory cell MCs constitute a memory cell array.
Each memory cell in a memory cell array comprises a source, a drain, a floating gate, and a control gate. Drains for memory cell MCs arranged on the same column (Y-axis direction) are commonly connected to a bit line in each cell for the corresponding columns. Control gates for memory cell MCs arranged on the same row (X-axis direction) are commonly connected to a word line for the corresponding rows. Sources for memory cell MCs are commonly connected to a source line SL in a given unit.
An X decoder (row decoder)
101
selects one of a plurality of the word lines (row selection). A Y decoder (column decoder)
102
selects one of a plurality of the bit lines in each cell.
A read circuit
103
senses data by reading data stored in a cell selected by the X decoder
101
and the Y decoder
102
. The read circuit
103
comprises a bit line BLL to which a cell-based bit line selected by Y decoder
102
is connected, a sense bit line BLS, a separation circuit
105
, a bias circuit
107
, a load circuit
109
, a sense line SA, and an amplifier circuit
110
. The separation circuit
105
comprises an N-channel separation transistor
104
. The separation transistor
104
is connected between the bit line BLL and the sense bit line BLS and electrically separates between the sense bit line BLS and the bit line BLL. The bias circuit
107
comprises an N-channel bias transistor
106
. The bias transistor
106
is connected between the sense bit line BLS and the sense line SA and optimizes voltages for memory cell MC's drains (the bit line BLL and the cell-based bit line BL) when data is read. The load circuit
109
uses a transistor
108
for a P-channel load which sets the sense line SA to a power supply voltage Vcc when data is read. During a sense period, the amplifier circuit
110
senses data by comparing a voltage generated on the sense line SA with a specified reference voltage VREF generated in a circuit (not shown).
The separation transistor
104
's gate is supplied with a control signal PART. The bias transistor
106
's gate is supplied with a bias voltage VBIAS which is lower than the power supply voltage Vcc.
The following describes a data read operation in the flash memory having the above-mentioned configuration with reference to a timing chart in FIG.
2
. As shown in
FIG. 2
, data is read in three basic periods: an address selection period, a sense period, and an output period.
The address selection period takes effect from when an external address change is received until the word line and the cell-based bit line are selected in a memory cell array. During this period, it is necessary to stabilize a bias voltage VBIAS supplied to the bias transistor
106
's gate. When the bias voltage VBIAS does not reach or exceeds a stable level during this period, the so-called soft-write effect occurs. By contrast, when the bias voltage VBIAS is lower than a stable level, bit line BLL charging delays. This is because the bias transistor
106
clamps the bit line BLL's voltage to a value which is lower than Vcc.
During the next sense period, the control signal PART turns on the separation transistor
104
and activates the amplifier circuit
110
at a timing when a memory cell is selected from the memory cell array. Before the separation transistor
104
turns on, a reset circuit (not shown) sets the bit line BLL to 0V. When the separation transistor
104
turn on, the bit line BLL becomes charged. Thereafter, a voltage VBLL of the bit line BLL varies with data stored for the selected memory cell. When the selected memory cell is set to “0”, this memory cell does not turn on even if the word line is selected and is activated. The VBLL rises to a high voltage. By contrast, when the selected memory cell is set to “1”, selecting the word line turns on this memory cell. The voltage VBLL lowers compared to the case where the data is set to “0”.
When the amplifier circuit
110
is activated, a sense line SA voltage VSA is compared with the reference voltage VREF to sense data for the selected memory cell. At this time, the reference voltage VREF is approximately set to a middle between a bit line BLL voltage when data is read from the memory cell set to “1” and a bit line BLL voltage when data is read from the memory cell set to “0”.
During the output period, data latched by the amplifier circuit
110
is sensed. This latched data is sent to an output circuit (not shown) and is output from an output pad (not shown).
As shown in
FIG. 2
, the bias voltage VBIAS stabilized after the address change temporarily drops when the sense period starts. The reason is described below.
FIG. 3
provides an enlarged view of changes in voltages VBLL and VSA for the bit line BLL and the sense line SA during the address selection period and the sense period with reference to a change of the bias voltage VBIAS in FIG.
2
.
The bit line BLL voltage VBLL is set to 0V when the control signal PART is activated and the separation transistor
104
turns on. The bit line BLL voltage VBLL is first charged when the sense period starts and the separation transistor
104
turns on.
The sense line SA voltage VSA is stable with a given value (Vcc−Vthp) till the sense period, where Vthp is a threshold value of a P-channel MOS transistor. When the sense period starts, the sense line SA voltage VSA drastically drops. This is because turning on the separation transistor
104
charges a large capacity parasitically given to the bit line BLL. Accordingly, the sense line SA voltage VSA drops down to almost the same level as the bit line BLL voltage VBLL. The bias voltage VBIAS temporarily drops under the influence of this bit line voltage drop.
This is described in more detail with reference to equivalent circuit diagrams in
FIGS. 4A through 4D
.
FIG. 4A
shows each transistor state and each node voltage state at a final stage of the address selection period. The bit line BLL remains set and maintains its voltage VBLL to 0V. The sense line SA remains in an initial state and maintains its voltage VSA to (Vcc−Vthp). The bias voltage VBIAS already reaches a stable state. The load transistor
108
charges the sense bit line BLS approximately up to (VBIAS−Vth), where Vth is a threshold value of the bias transistor
106
. At this time, the bias transistor
106
's source voltage (VBLS) rises to (VBIAS−Vth) which turns off the bias transistor
106
itself. Accordingly, the bias transistor
106
remains off. Since the control signal PART is inactive, the separation transistor
104
is also off.
FIG. 4B
shows each transistor state and each node voltage state when the sense period starts. When the control signal PART is activated and the separation transistor
104
turns on, an electric charge accumulated for the sense line SA and the sense bit line BLS is shared with a large

Affiliated with

Also associated with

Rating

Nonvolatile semiconductor memory device with initialization... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory device with initialization..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device with initialization... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3026805