Phase-locked loop having a stable damping factor

Details Phase-locked loop having a stable damping factor Phase-locked loop having a stable damping factor

2000-10-12

2003-04-29

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S175000, C331S185000, C331S057000

Reexamination Certificate

active

06556088

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates in general to a phase-locked loop, more particularly to an integrated phase-locked loop (PLL), featuring a damping which is practically independent of the process quality condition of the integrated PLL circuit components, temperature as well as supply voltage functions and noise incurred by the substrate of the integrated circuit.
Phase-locked loops are used to set the frequency f of an oscillator so that it agrees with the frequency f
0
of a reference oscillator without the phase shift between the two frequencies running away.
FIG. 1
shows the typical configuration of a known phase-locked loop. A phase detector
10
compares the phase of the PLL output signal f to that of the reference signal f
0
. Depending on whether the PLL output signal f leads or trails the reference signal of the phase detector outputs a signal UP or DOWN, prompting the charge pump
12
to apply or remove a charge to/from the low-pass filter
14
. The low-pass filter
14
generates a control voltage Vs proportional to the phase shift, this control voltage being applied to a voltage-controlled oscillator (VCO). The VCO oscillates such that—where necessary in conjunction with an output frequency divider
18
—a signal is output whose frequency varies in accordance with the VCO control voltage applied to the low-pass filter
14
and which in conclusion agrees with the frequency of the reference signal f
0
. Phase-locked loops of the type as shown in
FIG. 1
in which a charge pump is employed read e.g. from the paper “Charge Pump Phase-Locked Loops” by Floyd M. Gardner in IEEE Transactions on Communications, Vol. COM-28, No. 11, Nov 1980.
In current increasingly fast digital circuitry ring oscillators are used preferably as PLL VCOs, these ring oscillators consisting of a cascaded series arrangement of identical inverter circuits with direct feedback of the output to the input. In this arrangement the oscillation frequency of the signal output by the ring oscillator depends on the transit time in the individual inverter stages which can be set via control voltages applied to the individual inverter stages which as a rule are not directly controlled by the output voltage of the PLL low-pass filter but by a special bias generator which receives the output voltage of the low-pass filter as the input voltage and generates therefrom one or more control voltages which are applied to the individual inverter stages to set the transit time of the individual inverter stages and thus the frequency of the VCO output signal.
FIG. 2
shows one such known circuit comprising a bias generator
20
and ring oscillator in which the bias generator
20
receives the input voltage Vc and generates therefrom the two control signals VBP and VBN which control the transit time in the three inverter differential stages
22
,
24
and
26
of the ring oscillator and thus the frequency of the output signal of the ring oscillator. The output signal (UA
1
, UA
2
) of the ring oscillator is applied to the phase detector or a frequency divider where necessary in a further processed form. One such phase-locked loop including a ring oscillator and bias generator reads from the paper “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques” by John G. Maneatis in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 31, No. 11. November 1996, this paper being cited hereinafter as “Maneatis” for the sake of simplicity.
Maneatis describes a special inverter stage and a bias generator specially adapted thereto, the object of which is to reduce the dependencies of the VCO amplification factor K
0
and thus the damping z and natural frequency vn on the process-inherent fluctuations in the parameters of the PLL circuit components, the temperature as well as on the fluctuations in the supply voltage and noise introduced by the substrate of the integrated circuit. The VCO amplification factor K
0
is defined by the following equations:
K0
=
ⅆ
w
ⅆ
Vs
⁢
 
⁢
or
(1a)
K0
′
=
ⅆ
f
ⅆ
Vs
(1b)
where f is the PLL output frequency, v is the corresponding angular frequency and Vs is the output voltage furnished by the low-pass filter in conjunction with the charge pump controlled by the phase detector (see FIG.
1
).
FIG. 3
shows the inverter differential stage of the ring oscillator described in the cited Maneatis paper. Contained in each of the two branches in the inverter differential stage is a resistance RP and RN resp. each simulated by two PMOS FETs namely MPR
1
, MPR
2
and MPR
3
, MPR
4
resp., whose source/drain circuits are connected in parallel, one in each case (MPR
1
and MPR
4
resp.) being circuited as a diode whilst the other (MPR
2
and MPR
3
resp.) is gated by the bias voltage VBP. The resistances are connected to the differential outputs VAUSP and VAUSN resp. cascading the inverter differential stages, and to the source/drain circuit of the NMOS FETs MNS
1
and MNS
2
resp. acting as switches, receiving at each gate the input differential voltages VINN and VINP resp. from the preceding cascade inverter differential stage. The differential outputs VAUSP and VAUSN resp. are connected to the output capacitances CAUSP and CAUSN resp. defined by the gating surface of the NMOS FETs MNS
1
and MNS
2
resp. of the next inverter stage as well as by the length of the supply leads. Both branches of each inverter differential stage receive a current 2 Id furnished by a voltage-controlled current source made up of an NMOS FET MNIS gated by the bias voltage VBN. The bias voltages (=control voltages) VBP and VBN applied to each inverter differential stage of the ring oscillator are generated by the bias generator as shown in
FIG. 5
to be explained later.
In operation of the inverter differential stage the switch MNS
1
is periodically opened and closed, the switch MNS
2
assuming the other switching condition every time. When e.g. MNS
1
has just been closed, the capacitance CAUSP is charged until Id * RP=VAUSP where VAUSP is the voltage applied to the output VAUSP of the inverter differential stage. During this time the capacitance CAUSN is discharged until VAUSN=0 V. At the point of intersection of the voltages VAUSP and VAUSN the switching position of the switches MNS
1
, MNS
2
of the next inverter differential stage changes so that the transit time td of each inverter differential stage is given by
td=R
eff*
C
eff*1
n
2  (2)
where Reff is the resistance of Rp and Rn resp. and Ceff corresponds to the capacitances CAUSN and CAUSP.
The frequency f of the ring oscillator is then given by the following
f
=
1
2
*
n
*
td
=
1
2
*
n
*
Reff
*
Ceff
*
ln2
(
3
)
where n is the number of inverter differential stages of the ring oscillator.
FIG. 4
shows how a linear resistance is simulated for two different control voltages VBP (1.75 V and 2.5 V) by the two PMOS FETs of the “symmetrical” resistances RP and RN resp. in passing through the voltage difference “supply voltage (Vdd)—VBP” during an oscillation of the output voltage of an inverter stage. In this arrangement-the I/U characteristic is not linear, it instead being symmetrical about the point (VBP/2, Id) dividing the straight line connecting the origin and the point (VBP, 2Id) of the I/U in the middle. In this arrangement at VBP, 2Id a so-called effective resistance Reff materializes which describes the resistance effective for the oscillation of the oscillator stage and is given by:
R
eff=
nc*RPMOS
(
VBP
)  (4)
where RPMOS(VBP) is the resistance resulting from the local slope of the I/U curve at the point VBP/2Id and nc is a correction factor describing the ratio of RPMOS(VBP) to Reff. The principle of “symmetrical” resistances is likewise explained in Maneatis.
For the principle of “symmetrical” resistances to function the bias generator needs to set the bias voltage VBN of the current sources formed by the MOS FETs MNIS so that an inverter stage current 2Id always materializes which biases the lower limit of the voltage swing executed by the output voltage of

Affiliated with

Also associated with

Rating

Phase-locked loop having a stable damping factor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase-locked loop having a stable damping factor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop having a stable damping factor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3025951