Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-11-30
2003-05-13
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S030000, C345S042000, C345S048000, C345S051000, C345S055000
Reexamination Certificate
active
06563478
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electro-optical device such as a liquid crystal display device or the like, a driving method for the electro-optical device, an image processing circuit therefore, and electronic equipment using the electro-optical device as a display unit.
2. Description of Related Art
A related electro-optical device, for example, an active matrix liquid crystal display device will be described with reference to FIG.
15
and FIG.
16
.
As shown in
FIG. 16
, a liquid crystal display device consists mainly of a liquid crystal display panel
100
, a timing circuit
200
, and an image signal processing circuit
300
. The timing circuit
200
outputs a timing signal to be employed in respective units. A phase development circuit
301
included in the image signal processing circuit
300
inputs an image signal VID of one channel, develops it into image signals exhibiting N phases (N=6 in
FIG. 15
) of the image signal VID, and outputs the image signals. The image signal is developed into image signals exhibiting N phases thereof is to extend an application time during which a sampling circuit, to be described later, applies an image signal to each thin-film transistor. Consequently, it is intended to ensure long sampling time and charging/discharging time for a data signal applied to a thin-film transistor (TFT) panel.
An amplification/reversal circuit
302
reverses the polarity of image signals according to a criterion described below, amplifies the signals, and feeds the signals as image signals VID
1
to VID
6
exhibiting different phases to the liquid crystal display panel
100
. The polarity of image signals being reversed means that the voltage levels of the image signals are alternately reversed with the potentials at the half points of the peak pulse amplitudes thereof as reference potentials. Whether or not to reverse the polarity of the image signals is determined according to a criterion described below. Specifically, the criterion is whether an adopted data signal application form defines that the polarity of image signals should be reversed (1) for each scanning line, (2) for each data signal line, or (3) for each pixel location. A cycle of reversal is set to one horizontal scanning period or a dot cycle. This related art will, for convenience, be described on the assumption that the criterion is whether an adopted data signal application form defines that the polarity of image signals should be reversed (1) for each scanning line.
Moreover, a pre-charging signal NRS produced by the timing circuit
200
is a reverse signal, that is, a polarity-reversed signal, and fed to the liquid crystal display panel
100
.
Next, the liquid crystal display panel
100
will be described below. The liquid crystal display panel
100
has an element substrate and an opposite substrate opposed to each other while being spaced from each other. The space is filled with a liquid crystal. The element substrate and opposite substrate are formed with quartz substrates or made of a hard glass or the like.
On the element substrate, a plurality of scanning lines
112
is laid down parallel to an X direction in
FIG. 16
, and a plurality of data lines
114
are arranged in a Y direction orthogonal to the X direction. The data lines
114
are grouped in groups of six into blocks B
1
to Bm. Hereinafter, the data lines are generically referred to as the data lines
114
or discretely referred to as the data lines
114
a
to
114
f.
At the intersections between the scanning lines
112
and data lines
114
, gates of thin film transistors (TFTs)
116
serving as switching elements are connected on the scanning lines
112
, sources thereof are connected on the data lines
114
, and drains thereof are connected to pixel electrodes
118
. Each pixel location is composed of the pixel electrode
118
, a common electrode formed on the opposite substrate, and the liquid crystal clamped between the electrodes. The pixel locations are arranged in the form of a matrix at the intersections between the scanning lines
112
and data lines
114
. A holding capacitor (not shown) is connected to each pixel electrode
118
.
A scanning line drive circuit
120
formed on the element substrate places a pulsating scanning line signal sequentially on the scanning lines
112
according to a clock signal CLY output from the timing circuit
200
, a reverse clock signal CLY
INV
, and a transfer start pulse DY. Specifically, the scanning line drive circuit
120
shifts the transfer start pulse DY fed initially during a vertical scanning period from one stage therein to another in synchronous with the clock signal CLY or reverse clock signal CLY
INV
, and thus outputs the scanning line signal sequentially to the scanning lines
112
. Consequently, the scanning lines
112
are selected sequentially.
A sampling circuit
130
has sampling switches
131
connected to ends of the data lines
114
, and thus has the sampling switches
131
associated with the data lines
114
. The switches
131
are realized with n-channel TFTs formed on the element substrate. Image signals VID
1
to VID
6
are applied to the sources of the switches
131
. Six switches
131
connected on data lines
114
a
to
114
f
belonging to a block B
1
have the gates thereof connected on a signal line on which a sampling signal S
1
is placed. Six switches
131
connected on data lines
114
a
to
114
f
belonging to a block B
2
have the gates thereof connected on a signal line on which a sampling signal S
2
is placed. Likewise, six switches
131
connected on data lines
114
a
to
114
f
belonging to a block Bm have the gates thereof connected on a signal line on which a sampling signal Sm is placed. The sampling signals S
1
to Sm are signals used to sample the image signals VID
1
to VID
6
for each block during a horizontally effective display period.
Moreover, a shift register circuit
140
formed on the element substrate outputs the sampling signals S
1
to Sm successively in synchronous with the clock signal CLX output from the timing circuit
200
or the reverse clock signal CLX
INV
according to the transfer start pulse DX. To be more specific, the shift register circuit
140
shifts the transfer start pulse DX fed initially during a horizontal scanning period from one stage therein to another in synchronous with the clock signal CLX or reverse clock signal CLX
INV
. The shift register circuit
140
narrows the pulse duration of each resultant pulsating signal so that the pulse duration will not be the same between adjoining signals. Consequently, the shift register circuit
140
outputs the sampling signals S
1
to Sm successively.
In the foregoing configuration, when the sampling signal S
1
is output, the image signals VID
1
to VID
6
are sampled and applied to the six data lines
114
a
to
114
f
belonging to the block B
1
. The image signals VID
1
to VID
6
are written in six pixel locations defined along a currently-selected scanning line by the TFTs
116
associated with the pixel locations.
Thereafter, when the sampling signal S
2
is output, the image signals VID
1
to VID
6
are sampled and applied to the six data lines
114
a
to
114
f
belonging to the block B
2
. The image signals VID
1
to VID
6
are written in six pixel locations defined along the currently-selected scanning line by the TFTs
116
associated with the pixel locations.
Likewise, when the sampling signals S
3
, S
4
, . . . , Sm are output successively, the image signals VID
1
to VID
6
are sampled and applied to the six data lines
114
a
to
114
f
belonging to the block B
3
, B
4
. . . , Bm respectively. The image signals VID
1
to VID
6
are written in six pixel locations defined along the currently-selected scanning line. Thereafter, the next scanning line is selected, and writing is repeated in the same manner as that mentioned above relative to the blocks B
1
to Bm.
SUMMARY OF THE INVENTION
According to the foregoing driving method, the number of stages in the shift register ci
Oliff & Berridg,e PLC
Seiko Epson Corporation
Shalwala Bipin
Shapiro Leonid
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