Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2002-03-05
2003-04-22
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S072000, C257S435000
Reexamination Certificate
active
06552362
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a circuit comprising a thin film transistor (abbreviated as TFT hereinafter) formed by using a semiconductor thin film. In particular, it relates to a technique of a constitution of an auxiliary capacitance formed in each pixel of an active matrix type liquid crystal display device.
The semiconductor device used herein means any device that can function utilizing semiconductor characteristics, and involves an electro-optical device, such as the liquid crystal display device, and an electronic device carrying the display device.
2. Background Art
In recent years, an active matrix type liquid crystal display device comprising a circuit constituted with a thin film transistor (called TFT hereinafter) utilizing a polysilicon film receives attention. In the display device, an electric field applied on a liquid crystal is controlled in a matrix form by plural pixels arranged in a matrix form, so as to realize display of an image of high precision.
In the active matrix type liquid crystal display device, a capacitance (condenser) is formed between a pixel electrode provided for each pixel and a counter electrode formed on the opposite side of the pixel electrode via a liquid crystal. Because the capacitance is not large enough only by such a constitution, the capacitance is generally supplied by forming an auxiliary capacitance (sometimes called Cs).
For example, a structure has been known, in which capacitance wiring is formed on the same layer with the same material as the gate electrode, and an auxiliary capacitance is formed between the capacitance wiring and a part of an active layer (called a capacitance forming part) with a gate insulating film as a dielectric material.
In this structure, however, electric conductivity should be previously endowed to the capacitance forming part by adding an impurity before forming the capacitance wiring. That is, when a step of addition of an impurity is conducted after forming the capacitance wiring, the impurity is not added to the capacitance forming part, and thus it does not function as a capacitance electrode. Therefore, this structure cannot utilize advantages of the process, in which a source region and a drain region are formed in a self-aligning.
Another proposal has been made to solve such a problem in that a capacitance forming part, to which no impurity is added, is utilized as an electrode. That is, a constant voltage is always applied to the capacitance wiring, so that a channel region is always formed in the capacitance forming part, and the channel region is used as an electrode. However, this constitution is not preferred since it brings about increase in consuming electric power of the liquid crystal display device.
Accordingly, in a liquid crystal display device utilizing a top-gate TFT produced by a self-matching process as pixel TFT, a method of forming an auxiliary capacitance effectively utilizing the self-aligning process has not yet been developed.
SUMMARY OF THE INVENTION
An object of the invention is to provide an electro-optical device having a high aperture ratio, in which each pixel has a large auxiliary capacitance, and a process for producing the same. Another object of the invention is to provide an electronic device carrying the electro-optical device as a display.
The invention relates to, as a first aspect, a semiconductor device comprising a structure, in which each of plural pixels arranged in a matrix form has a top-gate TFT and an auxiliary capacitance, wherein
The auxiliary capacitance has a structure, in which a tantalum oxide film is sandwiched with a tantalum film and a semiconductor thin film; the semiconductor thin film constitutes a part of an active layer of the top-gate TFT; and the tantalum film is formed below beneath the semiconductor thin film.
The invention also relates to, as a second aspect, a semiconductor device comprising a structure, in which each of plural pixels arranged in a matrix form has a top-gate TFT and an auxiliary capacitance, wherein
The auxiliary capacitance has a structure, in which a laminated film comprising a tantalum oxide film and an insulating film containing silicon is sandwiched with a tantalum film and a semiconductor thin film; the semiconductor thin film constitutes a part of an active layer of the top-gate TFT; and the tantalum film is formed below the semiconductor thin film.
In the first and second aspect of the invention, the tantalum oxide film is formed by heat oxidation of the tantalum film. While the tantalum oxide film can be formed by an anodic oxidation method in addition to the heat oxidation method, the heat oxidation film and the anodic oxidation film are different in withstanding voltage from each other, and these can be easily distinguished by electric evaluation.
The invention further relates to, as a third aspect, a process for producing a semiconductor device, the process comprising
a step of forming capacitance wiring comprising a tantalum film on a substrate having an insulating surface,
a step of forming a tantalum oxide film on a surface of the capacitance wiring by a heat oxidation method, and
a step of forming a semiconductor thin film to cover the tantalum oxide film, wherein
the process comprises a step of producing a top-gate TFT using the semiconductor thin film as an active layer.
The invention further relates to, as a fourth aspect, a process for producing a semiconductor device, the process comprising
a step of forming capacitance wiring comprising a tantalum film on a substrate having an insulating surface,
a step of forming a tantalum oxide film on a surface of the capacitance wiring by a heat oxidation method,
a step of forming a semiconductor thin film to cover the tantalum oxide film,
a step of forming a gate insulating film and a gate electrode on the semiconductor thin film, and
a step of forming a source region and a drain region by adding an impurity element using the gate electrode as a mask.
In the third and fourth aspects of the invention, the heat oxidation method is generally conducted in a temperature range of from 450 to 600° C. One of the characteristic features of the invention resides in that the heat treatment for forming the tantalum oxide is conducted before the formation of an active layer/gate insulating film interface, which is sensitive to heat. Furthermore, because the heat treating step, is conducted at a relatively low temperature of from 450 to 600° C., a problem such as warp of glass does not occur even when the device is formed on a glass substrate.
REFERENCES:
patent: 4759610 (1988-07-01), Yanagisawa
patent: 4948231 (1990-08-01), Aoki et al.
patent: 4984033 (1991-01-01), Ishizu et al.
patent: 5087113 (1992-02-01), Sakono et al.
patent: 5121236 (1992-06-01), Ukai et al.
patent: 5510916 (1996-04-01), Takahashi
patent: 5672888 (1997-09-01), Nakamura
patent: 5708485 (1998-01-01), Sato et al.
patent: 5942310 (1999-08-01), Moon
patent: 6259200 (2001-07-01), Morita et al.
Fujimoto Etsuko
Ohtani Hisashi
Jackson Jerome
Robinson Eric J.
Robinson Intellectual Property Law Office, p.c.
Semiconductor Energy Laboratory Co,. Ltd.
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