Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-08-30
2003-04-08
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S751000, C257S762000, C257S771000, C438S652000, C438S653000, C438S672000, C438S688000
Reexamination Certificate
active
06545362
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
A semiconductor device has been miniaturized in recent years. As miniaturization has proceeded, the width of metal wiring lines in the device has narrowed, and, therefore, an aluminum comprising copper of about 0.5% by weight is generally used to prevent disconnection of a wire, or a hillock, in an aluminum wiring line due to migration.
However, in the case of the aluminum wiring line containing copper, there is a case where copper atoms are precipitated. The location of precipitation is around a grain boundary or an interface between an adjacent conductor layer and a main wiring layer. Especially, when a precipitate become large around the interface, there is a case where the precipitates remain there since the precipitate is not etched. In the case where a wiring interval (space between wirings) is narrow, it is a cause of short circuit failure between adjacent wiring lines.
Since there is a tendency that not only a width of the wiring line but also an interval between wiring lines narrow, the problem of short circuit failure can be serious. Then, for example, Japanese Patent Laid Open No. 186175/1996 discloses a method in which after forming an aluminum film and dissolving copper into the aluminum at high temperature, rapid pooling is carried out to prevent copper precipitates at the cooling.
SUMMARY OF THE INVENTION
To prevent short circuit failure between wiring lines, the method of manufacturing an aluminum wiring line containing copper by rapid cooling treatment is not satisfactory in the case where the semiconductor device has less than a 0.4 &mgr;m interval between wiring lines. In order to prevent short circuit failure between wiring lines, especially, it should be prevented that copper precipitates around the interface between an adjacent conductive layer and an aluminum wiring layer.
Therefore, an object of the present invention is to provide a semiconductor device having a wiring structure in which a short circuit can be avoided.
Furthermore, another object of the present invention is to provide a semiconductor device having high reliability.
Another object of the present invention is to provide a semiconductor device having high productivity.
A semiconductor device of the present invention comprises a semiconductor substrate, a wiring line overlying a main surface of said semiconductor substrate, and an insulating layer adjacent the wiring line. The wiring line has a main wiring layer, and the main wiring layer has a main constituent element and an added material (e.g., element). The concentration of the added material at a first portion in the main wiring layer is higher than that at a second portion, the second portion being closer to the insulating layer than said first portion of the main wiring layer is to the insulating layer. Desirably, the wiring line includes the main wiring layer and an adjacent conductor layer located between the main wiring layer and the insulating layer, and the second portion of the main wiring layer, having the lower concentration of the added material than the first portion, is closer to the interface of the main wiring layer and adjacent conductor layer than the first portion is to this interface.
Besides, a semiconductor device of the present invention includes a semiconductor substrate, a wiring line overlying a main surface of the semiconductor substrate, and an insulating layer adjacent the wiring line. The wiring line has a main wiring layer and, e.g., an adjacent conductor layer located between the main wiring layer and the insulating layer. The main wiring layer can be made of aluminum as a constituent (main) material and copper as an added material, and the adjacent conductor layer can be made of titanium or titanium nitride as a constituent material. Illustratively, as an alternative the constituent (main) element of the main wiring layer can be copper, with nickel as the added material; moreover, the adjacent conductor layer can be made of ruthenium. The concentration of the added material in a first portion in the main wiring layer is higher than that in a second portion located closer to the interface with the adjacent conductor layer than the first portion of said main wiring layer is to this interface.
Besides, a semiconductor device of the present invention comprises a semiconductor substrate, a wiring line on a main surface of said semiconductor substrate, and an insulating layer adjacent said wiring line. The wiring line has a layered structure. The layered structure has a layered main wiring layer and, e.g., an adjacent conductor layer located between said main wiring layer and said insulating layer. Said layered main wiring layer has a first main wiring layer, and a second main wiring layer located between said first main wiring layer and said adjacent conductor layer. A concentration of added material in said first main wiring layer is higher than that in said second main wiring layer.
Furthermore, the semiconductor device of the present invention can have the following: the concentration of copper in said first main wiring layer or first portion can be 0.4% by weight or more, and the concentration of said copper in said second wiring layer can be from 0% to 0.2% by weight (including the end points). Illustratively, and not to be limiting, the high-concentration portion of the wiring layer can have up to 5% by weight copper.
Besides, a semiconductor device of the present invention includes a semiconductor substrate, a wiring line overlying a main surface of the semiconductor substrate, and an insulating layer formed adjacent the wiring line. The wiring line has a layered structure. The layered structure has a layered main wiring layer and an adjacent conductor layer located between said main wiring layer and said insulating layer. Said main wiring layer has a first main wiring layer and a second main wiring layer located between said first main wiring layer and said adjacent conductor layer. The thickness of said second main wiring layer is from 5 nm to 40 nm. Illustratively, and not to be limiting, the first main wiring layer can have a thickness of 50 nm or more, and 3000 nm or less.
Furthermore, the semiconductor device of the present invention can have the following: the thickness of said second main wiring layer is from 5 nm to 40 nm, or, a part of said wiring line is formed a smaller distance than 0.4 &mgr;m (e.g., illustratively, and not to be limiting, about 50 nm, based upon present manufacturing machine capabilities) from another part of the wiring line located separately from the first-mentioned part of the wiring line.
Furthermore, the semiconductor device of the present invention can have the following: the first main wiring layer and the second main wiring layer have a same material as a constituent (main) element.
Besides, a semiconductor device of the present invention comprises a semiconductor substrate, a conducting means for conducting electricity overlying a main surface of said semiconductor substrate, and a layer for insulating said conducting means adjacent said conducting means. Said conducting means has main conducting means for conducting electricity and, e.g., an adjacent conducting means for obstructing movement of constituent material and/or added material of said main conducting means to said insulating means and located between said main conducting means and said insulating means. Said main conducting means has first main wiring means for conducting electricity and second main wiring means for obstructing movement of said added material of said first main wiring means toward said adjacent conducting means through said second main wiring means.
In the semiconductor device of the present invention, for example, said conducting means may be the wiring line, said insulating means may be the insulating layer, said main conducting means may be the main wiring layer, said adjacent conducting means may be the adjacent conducting wiring layer, said f
Iwasaki Tomio
Miura Hideo
Moriya Hiroshi
Nishihara Shinji
Sahara Masashi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Magee Thomas
Thomas Tom
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