Timing adjusting circuit

Details Timing adjusting circuit Timing adjusting circuit

2002-04-17

2003-05-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S151000

Reexamination Certificate

active

06570418

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing adjusting circuit, and more particularly to that for automatically adjusting a set-up time and a hold time between a data signal and a clock signal that are input into a flip-flop.
2. Description of the Related Art
A flip-flop for use in a typical integrated circuit cannot read correct data unless a set-up time and a hold time involving a time difference between a rising timing of the input-clock signal and a change timing of the input data signal are satisfied.
Therefore, the timing adjustment is required to make by delaying the input data signal. One example of the conventional timing adjusting circuit is shown in FIG.
3
and will be described below.
As shown in
FIG. 3
, a flip-flop
2
is provided at an input former stage of a logical circuit for making various arithmetical operations in an integrated circuit
4
.
Also, a variable delay circuit
31
into which a data signal
21
is input is provided, its output signal being connected to a data input terminal of the flip-flop
2
, and a clock signal
22
is input into a clock input terminal of the flip-flop
2
.
A set-up timing and a hold timing between the data signal and the clock signal to be input into the flip-flop
2
are adjusted by changing the timing of the data signal
21
in the variable delay circuit
31
.
However, the conventional timing adjusting circuit as described above has a problem that it is difficult to make the timing adjustment if the signal rate is fast.
Also, in the case where a great number of input data signals are present, a number of variable delay circuits are required corresponding to the number of input data signals, resulting in a problem that the circuit size of the timing adjusting circuit is increased.
SUMMARY OF THE INVENTION
The present invention has been achieved in the light of the above-mentioned problems. It is an object of the invention to provide the timing adjusting circuit that can automatically adjust the set-up time and the hold time between the data signal and the clock signal to be input into the flip-flop in the integrated circuit even if the corresponding signal rate is fast, in which the circuit size can be reduced.
To accomplish the above object, according to a first aspect of the present invention, there is provided a timing adjusting circuit into which a clock signal and a data signal are input from the outside and from which the data signal delayed is output to the outside, the timing adjusting circuit comprising a variable delay circuit for inputting the data signal and outputting the data signal delayed in accordance with a value set by a delay value setting signal, a first flip-flop having a data input terminal for inputting the data signal output from the variable delay circuit and a clock input terminal for inputting an inverse signal of the clock signal that is frequency divided, a second flip-flop having a data input terminal with a fixed input and a clock input terminal for inputting a signal output from the first flip-flop, and a counter having a counter enable input terminal for inputting a signal output from the second flip-flop, the counter counting the clock signal at every plural periods, and sending an output count value as the delay value setting signal to the variable delay circuit.
Thereby, the variable delay circuit delays the data signal by an amount of count value, and outputs the data signal delayed to the outside, thereby accomplishing the object.
Further, according to a second aspect of the invention, there is provided the timing adjusting circuit, further comprising a first frequency divider for dividing the frequency of the clock signal into half, and an inverter for inverting the clock signal, wherein an inverse signal of the frequency divided clock signal is generated.
Thereby, the inverse signal of the clock signal frequency divided can be easily generated into the clock input terminal of the first flip-flop.
Also, according to a third aspect of the invention, there is provided the timing adjusting circuit, further comprising a second frequency divider for dividing the frequency of the clock signal into 1/N, wherein a output signal of the second frequency divider is input into the clock input terminal of the counter.
Thereby, the counter can count the clock signal at every N periods.
Also, according to a fourth aspect of the invention, there is provided the timing adjusting circuit, wherein a set-up time and a hold time of an external flip-flop are adjusted by passing an output signal of the variable delay circuit into a data input terminal of the external flip-flop.
Thereby, the set-up time and the hold time between the data signal and the clock signal to be input into the external flip-flop in the integrated circuit can be adjusted automatically.


REFERENCES:
patent: 4206485 (1980-06-01), Sakamoto
patent: 4516861 (1985-05-01), Frew et al.
patent: 6396321 (2002-05-01), Watanabe et al.

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