Multilayer alignment keys and alignment method using the same

Details Multilayer alignment keys and alignment method using the same Multilayer alignment keys and alignment method using the same

2001-01-16

2003-03-25

Young, Christopher G. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Registration or layout process other than color proofing

C257S797000

Reexamination Certificate

active

06537713

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 200006448, filed on Feb. 11, 2000, the contents of which are herein incorporated by reference in their entirety.
Background of the Invention
1. Field of the Invention
The present invention relates to a semiconductor manufacturing, and more particularly to a multilayer alignment key and an alignment method using the same.
2. Description of the Related Art
To increase integrated circuit density, integrated circuit feature sizes continue to decrease, which results in decreased line pattern size. Particularly, density of DRAM (Dynamic Random Access Memory) devices reaches giga bit areas and thus the size of cell elements, such as transistors and capacitors, is significantly decreased. Semiconductor manufacturing requires a series of processing steps. These processing steps include depositing a variety of material layers to form cell elements and metal interconnection. Such processing steps require formation of contacts for electrical connection between cell elements and metal interconnections.
The deposited layers are typically patterned into predetermined configurations using a photoresist layer that is patterned over the material layers by exposing the photoresist through a photomask or reticle. The photoresist is then developed to provide the pattern. Typically, the photomask or reticle has alignment marks (or keys) that are aligned to alignment keys formed on the substrate at the previous processing step. It is important to align one masking level to the previous level.
FIG. 1
is a top plan view of a DRAM cell. Referring to
FIG. 1
, an elliptic-like active region
12
is defined in a semiconductor substrate
10
, and a pair of gate patterns
14
run across the active region
12
. A bit line
16
b
runs outside of the active region
12
, intersecting the gate patterns
14
. The bit line
16
b
electrically contacts with the active region
12
between the gate patterns
14
at a common drain region through a bit line contact
16
a
. Storage electrodes are disposed over the bit line to be electrically connected to the both ends of the active region
12
outside of the gate patterns at source regions through storage electrodes contact plugs
18
. Such patterns are formed through photolithographic processes which include alignment and etching steps.
For alignment, it is important to form a contact hole for electrical connection between the upper pattern and the lower pattern. One example is the connection between the source region and the storage electrode. In
FIG. 1
, for the storage electrode contact, a contact hole is formed and a conductive material is deposited in the contact hole to form the contact plug
18
. At this time, it is necessary to exactly align the contact plug
18
to the active region, i.e., source region, to prevent a short or bridge with the gate patterns
14
or bit line
16
b.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide alignment keys and a method of using the alignment keys to align upper and lower patterns without causing a short or bridge.
In one aspect, the invention is directed to alignment keys for aligning multiple layers in an integrated structure. The keys are formed in multiple stacked layers on a substrate. Each of the multiple stacked layers includes at least one alignment key disposed in the layer along a first direction. One or more other alignment keys in one or more respective other layers are disposed along the first direction such that a plurality of alignment keys in a respective plurality of layers are in alignment.
In one embodiment, the alignment keys have a rod-like rectangular shape. The length of the alignment keys in one layer can be different from that of other alignment keys in other layers, thereby imposing a different alignment weight. Also, the number of alignment keys in different layers can be different, thereby imposing a different alignment weight in each alignment key.
In one embodiment, a portion of at least one alignment key in a first layer overlaps a portion of another alignment key in another layer. The amount of overlap between keys on multiple layers can be different at each layer.
The alignment keys can have a concave shape. Alternatively, the keys can have a convex shape.
Thus, a feature of the present invention is to form multilayer alignment keys. In general, each alignment key can be formed in a different layer in the same direction.
In accordance with another aspect, the present invention is directed to a method for making alignment keys on a substrate and determining an alignment position of the substrate. Multilayered alignment keys are formed on the substrate such that the alignment keys on multiple layers are arranged in the same direction such that multiple alignment keys on multiple layers are in alignment. Light is directed into the substrate with the multilayered alignment keys. Information is received from light that is incident upon the substrate and the alignment keys, i.e., light that is reflected and/or scattered from the substrate and/or the keys. The alignment position is determined using the received information.
In one embodiment, a broadband light is directed onto the entire area of the substrate in which the multilayered alignment keys are formed. In receiving the information related to the light, scattered and/or reflected light from the alignment keys in each layer is downward detected, and the detected light is converted to an electrical signal. A convolution is then performed on the electrical signal. In one embodiment, the downward detection is carried out at a predetermined interval in a discrete time manner. In one embodiment, the light is monochromatic light.
In one embodiment, in receiving the information, diffracted light from the alignment keys in each layer is detected. The number of alignment keys in each layer is determined using the diffracted light, and an alignment weight is imposed on each layer. An imaginary signal is introduced to each layer, and the appropriate alignment weight is applied to each imaginary signal.
In determining the alignment position, convolutions are performed on electrical signals obtained from each alignment key in different layers, and a relation in an X-Y coordinate system is obtained. A maximum Y value is obtained from the convolutioned electrical signal. A reference Y value that has a predetermined ratio with respect to the maximum Y value is determined. Two X values are obtained from the reference Y value in the convolutioned electrical signal, and a middle point of the two X values is determined as the alignment position. In one embodiment, the X axis of the relation represents the position of the alignment keys, and the Y axis represents the intensity of the electrical signals.


REFERENCES:
patent: 6248484 (2001-06-01), Sajan et al.

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