DLL circuit, semiconductor device using the same and delay...

Details DLL circuit, semiconductor device using the same and delay... DLL circuit, semiconductor device using the same and delay...

2001-04-06

2003-01-21

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S158000, C327S161000, C327S284000, C375S376000, C331SDIG002

Reexamination Certificate

active

06509776

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a DLL circuit, a semiconductor device and a phase delay control method.
2. Description of the Related Art
The operation of a semiconductor device such as a memory circuit, an interface circuit, and a CPU is controlled based on a reference clock signal externally supplied. In recent years, with speed-up of the semiconductor device, it is required that a memory circuit can operate correctly at high speed in about 400 MHz. For example, a synchronous DRAM carries out data output in synchronism with the reference clock signal. Such a synchronous DRAM must operate correctly in synchronism with the rising edge and falling edge of the clock signal with about 2.5-ns period. In other words, this means that it is necessary for the memory circuit to operate at the timing of half period of 1.25 ns.
The operation of the synchronous DRAM is controlled by internal clock signals generated based on the reference clock signal. However, in order to guarantee a correct high-speed operation, it is necessary that the phase of the external clock signal as the reference clock signal and the phase of the internal clock signal are coincident with each other or the phase difference of the external clock signal and the internal clock signal is strictly controlled. For the purpose, a DLL circuit is used.
That is, a variable delay circuit delays the external clock signal and outputs as an internal clock signal from the DLL circuit. The phase of the internal clock signal generated in this way and the phase of the external clock signal are compared by the phase comparing circuit, and a feedback phase control is carried out based on the phase shift quantity and the delay quantity of the variable delay circuit is adjusted. In this way, the phase of the internal clock signal is made coincident with the phase of the external clock signal.
A conventional example of such a DLL circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 11-127063). The structure of this conventional example is shown in FIG.
1
. Also, the operation is shown in
FIGS. 2A
to
2
E. Referring to
FIG. 1
, the external clock signal is supplied to a variable delay circuit
103
as a signal N
1
through an input buffer as shown in FIG.
2
A. The variable delay circuit
103
delays the signal N
1
based on a delay control signal N
8
from a delay control circuit
107
to generate a signal N
4
as shown in FIG.
2
C. The signal N
4
is outputted as the internal clock signal through an output buffer
109
. Also, the signal N
4
is supplied to a timing synchronizing circuit
101
.
Also, the signal N
1
is divided by a frequency divider
102
and is supplied to a phase comparing circuit
106
as the signal N
2
as shown in FIG.
2
D. The signal N
2
is also supplied to a timing synchronizing circuit
101
. The timing synchronizing circuit
101
outputs the signal N
2
as the signal N
5
in synchronism with the signal N
4
as shown in FIG.
2
D.
The signal N
5
is supplied to the phase comparing circuit
106
as the signal N
7
through an output dummy circuit
104
and an input dummy circuit
105
as shown in FIG.
2
E. The phase comparing circuit
106
compares the signal N
2
and the signal N
7
in phase and outputs a phase difference to a delay control circuit
107
. The delay control circuit
107
generates the delay control signal based on the phase difference from the phase comparing circuit
106
and outputs it to the variable delay circuit
103
as a signal N
8
.
The internal clock signal S
4
which has been subjected to phase control in this way is used for the control of the timing at which read data is outputted from the output buffer
109
, and is in synchronous with the reference clock signal IN. As above-mentioned, the operation frequency of the memory circuit is increased in recent years and the increase of the consumed power (average operating current) becomes a problem. Generally, in a logic circuit composed of CMOS transistors, the charging current and discharge current flow only when the data is switched, i.e., 0 and 1 of the data is switched. Therefore, it is the output buffer and an input buffer and an output dummy circuit and an input dummy circuit that consume the most of current in the DLL circuit of FIG.
1
.
Therefore, in the conventional example shown in
FIG. 1
, the reference clock signal N
1
is divided in frequency into ½ by the frequency divider
102
, so that the number of times of the phase comparison operation is reduced to ½. Therefore, the number of times of the switching operation of the dummy circuit is suppressed to ½ and can reduce power consumption.
The operation of the timing synchronizing circuit
101
will be described with reference to FIG.
1
. The timing synchronizing circuit
101
has a flip-flop circuit which inputs the signal N
2
obtained by frequency-dividing the signal N
1
(
FIG. 2B
) and the signal N
4
(
FIG. 2B
) obtained by delaying the signal N
1
. The timing synchronizing circuit
101
generates the signal N
5
(
FIG. 2D
) obtained by synchronizing a frequency-division signal of the signal N
1
with the signal N
4
.
FIGS. 2A
to
2
E show timing charts when the timing synchronizing circuit
101
operates normally.
However, the delay quantity from the variable delay circuit
103
changes in accordance with the phase difference between the signal N
1
and the signal N
4
. Therefore, the timing synchronizing circuit
101
takes synchronization between the signals which have no relation substantively. For this reason, there is caused the state in which the signal N
2
changes during a setup hold period of the flip-flop circuit of the timing synchronizing circuit
101
, i.e., the state in which the rising edge of the signal N
4
and the change point of the signal N
2
are approximately coincident with each other. As a result, a meta-stable state is caused in which the output of data
1
and the outputs of data
0
balance so that a middle voltage is outputted. Consequently, an unstable operating state is caused such as delay of the rising timing of the signal N
5
and the disappearance of a signal waveform.
The phase difference which causes such an erroneous operation occurs in the process of taking the synchronization of the signal N
1
and the signal N
4
. However, it is generally difficult to design to operate the timing synchronizing circuit
101
stably in the wide frequency range.
In conjunction with the above description, a semiconductor integrated circuit with a phase comparing circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-209857). In the semiconductor integrated circuit of this reference, a first control circuit frequency-divides a first signal into 1
(n is an integer more than 1) in response to a third signal. A second control circuit frequency-divides a second signal into 1
in response to the third signal. A phase comparing section compares the output signal of the first control circuit and the output signal of the second control circuit in phase.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a DLL circuit which can reduce the power consumption.
Another object of the present invention is to provide a DLL circuit which can operate stably even if the frequency of an external clock signal changes.
Still another object of the present invention is to provide a DLL circuit which can control the number of times of phase comparison.
Yet still another object of the present invention is to provide a DLL circuit which detects the phase of an input clock signal with respect to a delay signal and can guarantee a stable operation.
Also, another object of the present invention to provide a DLL circuit which can operates stably during a period from a time when the DLL circuit is started, namely, from an unlock state (the state that the phase difference between the external clock signal and the internal clock signal does not fall within a predetermined range) to the lock state (the state that the phase

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