Multi-bank semiconductor memory device

Details Multi-bank semiconductor memory device Multi-bank semiconductor memory device

2001-02-26

2003-07-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S189090

Reexamination Certificate

active

06597621

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to a multi-bank semiconductor memory device having a plurality of banks. More specifically, the invention relates to a multi-bank DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a plurality of banks are provided for improving data access efficiency.
FIG. 25
is a schematic diagram showing an entire structure of a conventional multi-bank DRAM Referring to
FIG. 25
, DRAM
900
includes banks BK#A and BK#B. Bank BK#A includes a memory array
902
a
having memory cells (not shown) arranged in rows and columns and word lines WL (
0
)-WL (m) arranged corresponding to respective memory cell rows, a row decoder
903
a
generating a row decode signal for designating a row in memory array
902
a
, and a word line driver for driving, into the selected state, a word line arranged corresponding to an addressed row according to the row decode signal from row decoder
903
a
. Memory array
902
a
includes a global data bus GDB provided in a direction intersecting word lines WL (
0
)-WL (m). Global data bus GDB is coupled to an input/output buffer
906
a.
Bank BK#B similarly includes a memory array
902
b
having memory cells (not shown) arranged in rows and columns and word lines WL (
0
)-WL (m) provided corresponding to respective memory cell rows, a row decoder
903
b
for decoding a row address signal to generate a row decode signal for specifying an addressed row, and a word line driver
904
b
for driving, into the selected state, a word line arranged corresponding to an addressed row in memory array
902
b
according to the row decode signal from row decoder
903
b
. Memory array
902
b
also includes a global data bus GDB provided in the direction intersecting word lines WL (
0
)-WL (m). Global data bus GDB of memory array
902
b
is coupled to an input/output buffer
906
b.
Input/output buffers
906
a
and
906
b
are both coupled to N-bit IO lines IO (
0
)-IO (N−1) to input/output N-bit data. Respective IO lines coupled to input/output buffers
906
a
and
906
b
are interconnected by internal data transmission lines IL (
0
)-IL (N−1). These internal data transmission lines IL (
0
)-IL (N−1) are coupled to a load circuit
907
to be precharged to a predetermined voltage level.
Input/output buffers
906
a
and
906
b
are also coupled to a group of N-bit data input/output terminals
910
.
A control circuit
905
is commonly provided to banks BK#A and BK#B. Control circuit
905
controls operations of banks BK#A and BK#B in accordance with an address signal (multi-bit address) ADD supplied to an address terminal
908
and a command CMD supplied to a command input terminal
909
. Specifically, when a bank address included in address signal ADD designates bank BK#A, for example, control circuit
905
generates a control signal necessary for an operation designated by command CMD to supply the generated signal to bank BK#A. For example, if command CMD designates array activation (word line selection) and a bank address included in address signal ADD designates bank BK#A, control circuit
905
activates row decoder
903
a
and word line driver
904
a
provided for bank BK#A. Accordingly, in memory array
902
a
, a word line corresponding to a row designated by address signal ADD is driven into the selected state.
If data access (data writing or reading) for bank BK#A is designated by address signal ADD and command CMD, control circuit
905
generates a control signal for activating input/output buffer
906
a
of bank BK#A to allow data to be transferred (written/read) between corresponding data bus GDB and data input/output terminal group
910
.
In the DRAM shown in
FIG. 25
, banks BK#A and BK#B are provided with respective row decoders for row selection and respective word drivers as well as respective input/output buffers for data input/output. If a row selecting circuit, a column selecting circuit (not shown) and the data input/output circuit are provided for each bank as is done in DRAM
900
, a possible problem is that increase in number of banks results in increase in chip area or area penalty of DRAM
900
.
In order to overcome such a problem of increase in chip area due to the structure having the row selection, column selection and data input/output circuits provided for each bank, a bank structure shown in
FIG. 26
is employed in an embedded DRAM for example formed on the same semiconductor chip as that of logic.
FIG. 26
is a schematic diagram showing an entire structure of a conventional embedded DRAM. In
FIG. 26
, embedded DRAM
950
includes banks BK#
0
and BK#
1
. Bank BK#
0
includes memory sub arrays
952
a
and
952
b
aligned in a row direction and a row selection circuit
954
a
for selecting rows in respective memory sub arrays
952
a
and
952
b
. Row selection circuit
954
a
includes a row decoder and a word line driver.
Bank BK#
1
includes memory sub arrays
952
c
and
952
d
aligned in the row direction, and a row selection circuit
954
b
provided between memory sub arrays
952
c
and
952
d
for selecting rows in respective memory sub arrays
952
c
and
952
d
. Row selection circuit
954
b
also includes a row decoder and a word line driver. Memory sub arrays
952
a
-
952
d
each include (m/2)+1 word lines WL (
0
)-WL (m/2).
A global data bus GDB is commonly provided to memory sub arrays aligned in the column direction. Specifically, a global data bus GDB coupled to an input/output buffer
956
a
is commonly provided to memory sub arrays
952
a
and
952
c
and a global data bus GDB coupled to an input/output buffer
956
b
is commonly provided to memory sub arrays
952
b
and
952
d
. These global data buses GDBs each have a bit width of N/2.
Input output buffer
956
a
is coupled to a group of data input/output nodes
960
a
with a bit width of N/2 through internal data lines IO<0> to IO<N/2−1> and input/output buffer
956
b
is coupled to a group of data input/output nodes
960
b
with a bit width of N/2 through internal data lines IO<N/2> to IO<N−1>.
A control circuit
958
is provided commonly to banks BK#
0
and BK#
1
for controlling operations of these banks BK#
0
and BK#
1
. Control circuit
958
receives an address signal ADD supplied to an address input node
962
and a command CMD supplied to a command input node
964
to generate a control signal necessary for an operation designated by this command signal CMD.
In the structure of the embedded DRAM shown in
FIG. 26
, input/output buffers
956
a
and
956
b
are shared by banks BK#
0
and BK#
1
Global data bus GDB is also shared by banks BK#
0
and BK#
1
Global data bus GDB has a bit width of N/2. Arrangement of banks BK#
0
and BK#
1
aligned in the column direction makes it possible to arrange the input/output buffers and global data buses commonly to these banks to reduce the chip area of the embedded DRAM.
In the bank structure as shown in
FIG. 26
, a word line must be selected in each of the two memory sub arrays aligned in the row direction. Compared with the bank structure shown in
FIG. 25
, the equivalent total length of a word line is made longer and a greater number of sense amplifiers are simultaneously activated. Resultant problems are increase in current consumption in row selection and increase in load of a boosted voltage source circuit generating a boosted voltage used for a word line drive signal transmitted to a selected word line.
It would be possible to reduce the power consumption of the embedded DRAM as shown in
FIG. 26
by activating only one memory sub array in a selected bank.
Specifically, as shown in
FIG. 27
, input/output buffers
956
a
and
956
b
are coupled commonly to a group of data input/output nodes
966
through the internal data bus

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